Stacked Channel Transistor Contacts With Alternating Doping Layers
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Solution Overview
Problem
The challenge of scaling down transistors in semiconductor devices while maintaining optimal operating characteristics, particularly in FinFETs, is addressed by the development of semiconductor devices with improved electrical characteristics through a specific structure and doping layers.
Innovation Solution
The semiconductor device incorporates a source/drain region with alternating epitaxial and doping layers, each with distinct impurity concentrations and thicknesses, and a contact plug that ensures consistent contact with the doping layers, reducing contact resistance and preventing impurity diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistors are scaled down to increase integration density, then device size is reduced, but operating characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating vertically stacked channel layers with different materials (e.g., Si, Ge, SiGe) and varying impurity concentrations at different heights. This allows each local region of the channel to have optimized properties for carrier transport, maintaining performance despite reduced lateral dimensions. The gate structure also implements local quality by providing different electric field distributions at various depths to optimize channel control.
Solution Approach 2:
The patent transitions from planar 2D channels to vertically stacked 3D channels, utilizing the vertical dimension to increase effective channel width without increasing lateral footprint. This dimensional change allows continued scaling in lateral directions while maintaining or improving electrical characteristics through the added vertical channel pathways.
2Reliability
If contact resistance is reduced by improving contact structure, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
The contact structure is segmented into multiple functional layers including barrier layers (e.g., TiN, WN), adhesion layers, and conductive layers (e.g., Cu, Al). Each layer performs a specific function: preventing diffusion, ensuring adhesion, or providing low-resistance conduction. This segmentation allows optimization of each interface separately, reducing overall contact resistance while managing complexity through modular design.
Solution Approach 2:
Barrier layers and adhesion layers serve as intermediaries between the metal contact and semiconductor materials. These intermediary layers prevent direct contact between incompatible materials, reducing diffusion and improving electrical characteristics. For example, a TiN barrier layer prevents Cu diffusion into the semiconductor while maintaining low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enhances the performance of semiconductor devices by reducing contact resistance and maintaining crystal integrity, thereby improving the overall electrical characteristics and integration density.
Implementation Method 1
doping layers stacked alternately with the second epitaxial layers, each doping layer including the impurities in a second concentration higher than the first concentration
Implementation Method 2
a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers; second epitaxial layers disposed on the first epitaxial layer
Data Source
AI summary
A semiconductor device includes an active region, a plurality of channel layers disposed to be spaced apart from each other in a vertical direction on the active region, a gate structure extending in a second direction to intersect the active region and the plurality of channel layers and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers, and a contact plug connected to the source/drain region. The source/drain region includes a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers, second epitaxial layers disposed on the first epitaxial layer, each including impurities in a first concentration, and doping layers stacked alternately with the second epitaxial layers, each including the impurities in a second concentration higher than the first concentration.