Stacked Channel Semiconductor Structure for Deep Source/Drain Etching
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving deep etching in reduced-size devices, leading to unetched source/drain issues and current leakage from the lower portions, which complicates the implementation of complex and reliable structures.
Innovation Solution
The semiconductor device incorporates a backside power distribution network (BSPDN) structure with a lower pattern layer having etching selectivity, allowing for deep etching and preventing current leakage by forming a bulk-less substrate configuration through selective etching, thereby enabling the creation of complex structures without productivity losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the device size is reduced, then the integration density is improved, but the etching depth capability deteriorates leading to unetched source/drain
Solution Approach 1:
The patent introduces a lower pattern layer as an intermediary sacrificial structure that enables deep etching access to the source/drain region. This layer is selectively removed to create the necessary etching pathway, allowing the etch to reach deep into the reduced-size device structure without being blocked by the substrate, thereby solving the unetched source/drain problem in scaled devices.
Solution Approach 2:
The patent changes the physical and chemical parameters of the lower pattern layer by using materials with specific etching selectivity (silicon, germanium, or carbon-containing materials). This parameter change allows selective removal of the lower pattern layer while preserving other device structures, enabling deep etching access in reduced-size devices without compromising manufacturing precision.
2Manufacturing precision
If deep etching is performed to etch source/drain, then the source/drain etching is improved, but current leakage from lower portions increases
Solution Approach 1:
The first conductivity-type doped pattern layer acts as an intermediary blocking structure that prevents current leakage. This layer is positioned to block the lower portion where current leakage occurs, while allowing the etch to penetrate through the lower pattern layer to properly etch the source/drain region. The doped structure provides both mechanical support and electrical isolation to prevent leakage.
Solution Approach 2:
The patent applies local quality by doping specific regions with different conductivity types. The first conductivity-type doped pattern layer is strategically doped to create local electrical properties that block current leakage in the lower portion, while the source/drain region maintains its own doping characteristics for proper device operation. This localized doping approach prevents leakage without compromising source/drain etching quality.
3Device complexity
If a BSPDN structure is implemented, then the device complexity is improved, but the manufacturing process complexity increases
Solution Approach 1:
The lower pattern layer serves a dual function: it acts as a sacrificial structure to enable deep etching and simultaneously serves as the foundation for the BSPDN structure. By integrating the power distribution network formation into the same etching and filling process, the patent avoids additional manufacturing steps, allowing complex BSPDN structures to be implemented without proportionally increasing manufacturing complexity.
Solution Approach 2:
The lower pattern layer and first conductivity-type doped pattern layer serve multiple functions: they enable deep etching access, prevent current leakage, and provide the structural foundation for the BSPDN. This multi-functionality reduces the number of separate manufacturing processes needed, allowing complex device structures to be manufactured with relatively simple processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively addresses the unetching and leakage issues, enabling the fabrication of complex semiconductor devices with improved reliability and reduced size, while maintaining performance and preventing productivity decreases.
Implementation Method 1
a lower pattern layer having etching selectivity, allowing for deep etching and preventing current leakage by forming a bulk-less substrate configuration through selective etching
Data Source
AI summary
Provided is a semiconductor device including a lower pattern layer including a first semiconductor material; a first conductivity-type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity; a channel pattern including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern.