Stacked Channel Semiconductor Structure With Epitaxy Blocking
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with high integration density and multifunctionality poses challenges in maintaining electrical properties and reliability due to the reduction in size of planar metal oxide semiconductor (FET) devices, particularly with the limitations of existing FinFETs and gate-all-around type field effect transistors.
Innovation Solution
A semiconductor device design featuring active patterns with multiple channel layers, intermediate insulating layers, and a gate structure that includes a blocking structure to prevent epitaxial growth, enhancing electrical properties and reliability by replacing traditional source/drain regions with blocking structures to prevent deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional source/drain regions are used in FinFET structures, then device integration density can be increased, but epitaxial growth occurs causing deterioration of electrical properties
Solution Approach 1:
The patent removes the traditional source/drain region from the FinFET structure and replaces it with a blocking structure. This extraction eliminates the harmful epitaxial growth that occurs in conventional source/drain regions, thereby preventing deterioration of electrical properties while maintaining high integration density through the stacked channel layer configuration.
Solution Approach 2:
The blocking structure serves as an intermediary element between the substrate and the channel layers. Instead of using conventional source/drain regions that cause epitaxial growth, the blocking structure mediates the connection while preventing the harmful growth, thus preserving electrical properties without sacrificing integration capability.
2Productivity
If planar metal oxide semiconductor FET size is reduced to increase integration density, then more devices can be integrated, but operating properties deteriorate
Solution Approach 1:
The patent transitions from a planar 2D channel structure to a 3D stacked channel layer configuration. By stacking multiple channel layers vertically, the device achieves higher integration density without reducing the effective channel dimensions in the lateral plane, thereby maintaining operating properties while increasing the number of devices that can be integrated.
Solution Approach 2:
The patent employs a composite structure consisting of multiple semiconductor layers with different materials (e.g., SiGe and Si layers) stacked together. This composite channel structure allows for optimized electrical properties through material engineering, maintaining performance while enabling higher integration density through the vertical stacking approach.
3Ease of manufacture
If floating epitaxial regions are present in the device structure, then manufacturing can be simplified, but electrical properties and reliability deteriorate
Solution Approach 1:
The patent converts the potential harm of epitaxial growth into a benefit by using the blocking structure to control and direct the epitaxial growth process. The blocking structure prevents unwanted epitaxial growth in critical regions while allowing controlled growth in other areas, thus eliminating the deterioration of electrical properties while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively improves electrical properties and reliability by preventing epitaxial growth, thereby addressing issues related to floating epitaxial regions and enhancing the performance of semiconductor devices.
Implementation Method 1
a blocking structure on a second side of the gate structure and connected to the lower channel layers
Data Source
AI summary
A semiconductor device includes an active pattern extending in a first direction; a plurality of channel layers spaced apart from each other on the active pattern in a vertical direction and including lower channel layers and upper channel layers; an intermediate insulating layer between an uppermost lower channel layer and a lowermost upper channel layer; a gate structure intersecting the active pattern and the plurality of channel layers, and extending in a second direction intersecting the first direction; a lower source/drain region on a first side of the gate structure and connected to the lower channel layers; a blocking structure on a second side of the gate structure and connected to the lower channel layers; and an upper source/drain region on at least one side of the gate structure.