Stacked Channel Semiconductor Structure With Etch-Stop Leakage Control
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and multifunctionality due to issues with etching the source/drain structures, leading to current leakage and complexity in device design.
Innovation Solution
A semiconductor device design that includes a lower pattern layer, a conductivity-type doped pattern layer, source/drain patterns, a channel pattern, and a gate pattern, where the lower pattern layer acts as an etch-stopping layer to prevent substrate etching and allows for a backside power distribution network structure, enabling deep etching and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If etching is performed to create source/drain structures, then device integration and functionality are improved, but current leakage occurs due to incomplete etching or substrate damage
Solution Approach 1:
The patent introduces an etch-stop layer positioned between the substrate and the source/drain structures. This intermediary layer prevents etching from penetrating into the substrate while allowing the formation of deep source/drain structures. The etch-stop layer acts as a mediator that enables complete source/drain etching without causing substrate damage or current leakage, thereby resolving the contradiction between achieving deep etching for device functionality and preventing current leakage for reliability.
2Adaptability or versatility
If device size is reduced to increase integration, then device complexity and functionality are improved, but etching depth becomes insufficient leading to unetched source/drain
Solution Approach 1:
The etch-stop layer serves as a mediator that enables precise control of etching depth in miniaturized devices. By providing a distinct stopping point for the etching process, it ensures that source/drain structures are completely formed even in reduced-size devices with deeper required etching depths, preventing unetched remnants that would compromise manufacturing precision.
Solution Approach 2:
The etch-stop layer is prepared in advance before the source/drain etching process. This preliminary action of placing the stop layer ensures that when etching is performed later, the process can proceed to the required depth without risk of over-etching or incomplete etching, thereby guaranteeing manufacturing precision in miniaturized devices.
3Ease of manufacture
If traditional substrate structure is used, then manufacturing simplicity is maintained, but current leakage occurs from lower substrate portions
Solution Approach 1:
The etch-stop layer acts as an intermediary barrier that prevents current leakage from the substrate while maintaining a relatively simple substrate structure. Rather than fundamentally changing the substrate itself, the stop layer is added as a controlled intermediate structure that blocks leakage paths without significantly complicating the overall manufacturing process.
Solution Approach 2:
The substrate structure is segmented by introducing the etch-stop layer as a distinct functional layer. This segmentation separates the substrate from the source/drain structures and creates a dedicated barrier against current leakage, allowing the substrate to remain simple while achieving improved reliability through the added functional layer.
Data Source
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AI summary
Provided is a semiconductor device including a lower pattern layer including a first semiconductor material; a first conductivity-type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity; a channel pattern including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern.