Vertically Stacked Channel Layers for MOSFET Scaling
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in reliability and electrical characteristics.
Innovation Solution
A semiconductor device design featuring active patterns with vertically stacked channel layers, a gate electrode intersecting the active patterns, and active contacts with protruding portions that cover inclined source/drain pattern surfaces, along with a method of fabrication involving metal-induced crystallization and selective silicidation processes to form self-aligned contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then device density increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel layers. Multiple channel layers are stacked in the vertical direction (third direction) above the substrate, allowing increased device density without further lateral scaling. This dimensional change enables maintaining operational properties by providing multiple conduction paths while achieving higher integration density.
Solution Approach 2:
The gate electrode completely surrounds each channel layer in a nested configuration, with the gate wrapping around the channel from all sides. This gate-all-around structure provides superior electrostatic control over the channel compared to planar gates, enabling better operational reliability in the scaled-down vertical architecture.
2Reliability
If active contacts are formed to cover source/drain patterns, then electrical connection is improved, but contact dimensions must be precisely controlled
Solution Approach 1:
The active contacts are formed using a self-aligned process where the contact width is automatically defined by the gate electrode dimensions and positioning. The gate serves as its own alignment reference, eliminating the need for separate alignment steps and reducing manufacturing precision requirements. The contact width is self-regulated by the gate structure rather than requiring independent precise patterning.
Solution Approach 2:
The gate electrode is formed first as a reference structure before forming the active contacts. This preliminary action establishes the alignment baseline that automatically defines the contact dimensions and positions, ensuring proper coverage of source/drain patterns while simplifying subsequent contact formation.
3Productivity
If vertically stacked channel layers are implemented, then device density increases, but fabrication complexity increases
Solution Approach 1:
The vertical stack is segmented into discrete channel layers separated by insulating layers, with each layer independently controllable by the surrounding gate. This segmentation allows standard planar fabrication techniques to be adapted to vertical structures by repeating layer formation cycles, managing complexity through modular construction rather than monolithic complex processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and electrical characteristics of semiconductor devices by reducing electric resistance and increasing the margin between active and gate contacts, thereby improving the performance and fabrication efficiency.
Implementation Method 1
selectively forming a pair of silicide patterns on top surfaces of the pair of source/drain patterns
Implementation Method 2
forming a pair of preliminary active contacts through a metal-induced crystallization process based on the pair of silicide patterns
Data Source
AI summary
A semiconductor device includes an active pattern on a substrate, source/drain patterns on the active pattern, a plurality of channel layers stacked on the active pattern to be vertically spaced apart from each other and connecting the source/drain patterns with each other, a gate electrode between the source/drain patterns to cross the active pattern and to surround the channel layers, and active contacts at opposite sides of the gate electrode to cover top surfaces of the source/drain patterns. A width of each of the active contacts is smaller than or equal to the largest width of each of the source/drain patterns. Each of the top surfaces of the source/drain patterns has an inclined surface that is inclined relative to a top surface of the substrate, and each of the active contacts includes a protruding portion that protrudes toward the inclined surface.