Vertically Stacked Channel Semiconductor Device for Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, necessitating improved fabrication methods to enhance performance while overcoming integration limitations.
Innovation Solution
The semiconductor device incorporates a substrate with distinct regions and channel patterns, featuring vertically stacked semiconductor patterns and gate electrodes of varying widths and thicknesses, along with high-k dielectric layers of differing thicknesses to optimize electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration density, then device integration is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple channel patterns are stacked in the vertical direction to increase the effective channel width without increasing the lateral footprint, thereby maintaining high integration density while improving gate control and electrical characteristics through enhanced surface-to-volume ratio
Solution Approach 2:
The patent applies different gate electrode thicknesses to different functional regions: thicker gate electrodes in peripheral regions for high-voltage devices and thinner gate electrodes in logic cell regions for low-voltage devices. This localized differentiation allows each region to be optimized for its specific operating requirements, improving overall device performance while maintaining high integration
2Reliability
If gate electrode thickness is increased to improve gate control, then control capability is improved, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple channel patterns vertically. This increases the effective channel width and gate control capability without increasing the lateral device area, as the additional channels are arranged in the vertical direction rather than expanding the footprint
Solution Approach 2:
The patent implements variable gate electrode thicknesses tailored to specific functional regions. Thicker gate electrodes are applied only where high-voltage operation requires enhanced gate control, while thinner gate electrodes are used in logic cell regions where lower voltages are sufficient, thereby optimizing gate control capability without uniformly increasing device area
3Reliability
If high-k dielectric layer thickness is increased to reduce leakage current, then electrical performance is improved, but capacitance decreases
Solution Approach 1:
The patent employs different high-k dielectric layer thicknesses in different regions: thicker high-k dielectric layers in peripheral regions for high-voltage devices to reduce leakage current, and thinner high-k dielectric layers in logic cell regions for low-voltage devices to maintain sufficient capacitance. This localized optimization allows leakage reduction where needed while preserving capacitance where required
Solution Approach 2:
The patent uses composite gate dielectric structures combining high-k dielectric layers with interface dielectric layers. The high-k dielectric provides leakage reduction while the interface dielectric maintains good electrical interface properties and capacitance, creating a composite structure that balances both requirements
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including a peripheral region and a logic cell region, a first channel pattern including a first and a second semiconductor pattern stacked vertically on the peripheral region, a first gate electrode across the first channel pattern and extending in a first direction, a second channel pattern including a third and a fourth semiconductor pattern stacked vertically on the logic cell region, and a second gate electrode across the second channel pattern and extending in the first direction, the second gate electrode having a second width in a second direction less than a first width in the second direction of the first gate electrode. The first gate electrode has a first thickness between the first and the second semiconductor pattern, and the second gate electrode has a second thickness between the third and the fourth semiconductor pattern greater than the first thickness.