Stacked Channel Gate Dielectrics for MOSFET Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are scaled down, issues such as short-channel effects, parasitic capacitance, and off-state leakage current deteriorate, necessitating improved electrical characteristics and manufacturing methods to enhance performance and integration.
Innovation Solution
A semiconductor device design featuring transistors with stacked semiconductor channel layers, a layered gate structure comprising interfacial, high-κ, and composite dielectric layers, and a gate electrode, along with a method of manufacturing that includes forming these layers on a substrate to improve electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is reduced for scaling, then integration density is improved, but electrical characteristics such as short-channel effect, parasitic capacitance, and off-state leakage current deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to 3D vertically stacked channel layers, enabling increased integration density while maintaining effective gate control through the gate-all-around configuration that surrounds the vertical channels
2Ease of manufacture
If simple gate insulating layer is used, then manufacturing complexity is reduced, but electrical performance and leakage control are insufficient
Solution Approach 1:
The gate insulating layer employs a composite structure with multiple dielectric materials having different κ values stacked together, where the lower high-κ layer provides strong electric field control and the upper low-κ layer reduces parasitic capacitance, achieving superior electrical performance while using standard deposition processes
Solution Approach 2:
Different regions of the gate insulating layer have different dielectric properties - the lower portion near the channel uses high-κ material for strong control, while the upper portion uses low-κ material for capacitance reduction, optimizing performance at different locations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances electrical performance by reducing leakage current and improving reliability, allowing for high voltage resistance and fast operation while maintaining compatibility with existing processes.
Implementation Method 1
a lower high-κ dielectric layer containing a first metal element, a composite dielectric layer containing the first metal element and a second metal element different from the first metal element
Data Source
AI summary
A semiconductor device includes a first transistor on a first region of a substrate, and a second transistor on a second region of the substrate. The first transistor includes a first gate insulating layer including a first interfacial insulating layer, a first lower high-κ dielectric layer, and a first composite dielectric layer, sequentially stacked on each of first semiconductor channel layers. The second transistor includes a second gate insulating layer including a second interfacial insulating layer, a second lower high-κ dielectric layer, a second composite dielectric layer, and a second upper high-κ dielectric layer, sequentially stacked on each of second semiconductor channel layers. The first and the second lower high-κ dielectric layers include a first metal element, the second upper high-κ dielectric layer includes a second metal element, and the first and the second composite dielectric layers include both of the first and the second metal elements.