Stacked Channel Gate Structure for Dense Semiconductor Integration
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Solution Overview
Problem
As semiconductor devices become more integrated and miniaturized, they face challenges in maintaining high performance and reliability due to size reductions, particularly in operating characteristics and power delivery networks.
Innovation Solution
The semiconductor device incorporates a substrate insulating layer with a fin-type structure, including a lower insulating pattern, an intermediate insulating pattern, and a semiconductor pattern, with channel layers stacked perpendicular to the substrate surface, a gate structure intersecting the semiconductor pattern, and contact structures for improved electrical connectivity and power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are miniaturized and highly integrated, then integration density increases, but operating characteristics and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional stacked channel layers, enabling vertical stacking of multiple channels to increase integration density while maintaining effective channel control through gate structures that surround each channel layer, thus preserving operating characteristics despite miniaturization
Solution Approach 2:
The channel region is divided into multiple discrete channel layers stacked vertically, with each layer independently controlled by gate structures. This segmentation allows for better electrical isolation and control of each channel, improving reliability while achieving higher integration density through vertical stacking
2Productivity
If channel size is reduced for miniaturization, then device density increases, but channel control and electrical properties deteriorate
Solution Approach 1:
The invention introduces vertical stacking of channel layers, transforming the channel architecture from horizontal planar to vertical three-dimensional. This enables increased device density without reducing individual channel dimensions, as each stacked channel layer maintains adequate size for effective gate control while the vertical arrangement increases overall device capacity
Solution Approach 2:
Gate structures are designed to surround and enclose channel layers in a nested configuration, with gates positioned on multiple sides of each channel layer. This nested arrangement provides comprehensive gate control over the channel while maintaining compact dimensions, enabling better electrical properties despite miniaturization
3Ease of manufacture
If planar structure is used, then manufacturing is simpler, but power delivery and channel control are limited
Solution Approach 1:
The patent introduces vertical stacking of channel layers and corresponding gate structures, transitioning from planar to three-dimensional architecture. This vertical arrangement enables more efficient power delivery networks by reducing current path lengths and improving electrical connectivity, while the modular stacked design maintains manufacturing feasibility through standardized layer fabrication processes
Data Source
AI summary
A semiconductor device includes a substrate insulating layer having a lower insulating pattern protruding from an upper surface of the substrate insulating layer and extending in a first direction; a semiconductor pattern extending on the lower insulating pattern of the substrate insulating layer in the first direction; a plurality of channel layers stacked on the semiconductor pattern and spaced apart from each other in a direction perpendicular to the upper surface of the substrate insulating layer; a gate structure intersecting the semiconductor pattern, extending in a second direction crossing the first direction, and surrounding the plurality of channel layers; first and second source/drain regions disposed on the semiconductor pattern on both sides of the gate structure; and an intermediate insulating pattern disposed between the lower insulating pattern and the semiconductor pattern and having a thickness equal to or less than a distance between the plurality of channel layers.