Stacked Channel Gate Isolation Structure for Dense Semiconductor Integration
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Solution Overview
Problem
The increasing demands for high performance, speed, and multifunctionality in semiconductor devices require enhanced integration density and reliability, which existing semiconductor devices struggle to achieve effectively.
Innovation Solution
A semiconductor device design featuring vertically stacked channel layers with middle dielectric isolation structures, gate structures, and gate isolation insulating layers to increase integration density and reliability, including specific configurations of channel layers, gate electrodes, source/drain regions, and contact structures, enabling improved electrical insulation and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked channel layers are implemented to increase integration density, then the number of transistors per unit area increases, but electrical insulation between adjacent structures becomes more difficult to maintain
Solution Approach 1:
A gate isolation insulating layer is introduced as an intermediary structure between adjacent gate structures (first gate structure and second gate structure) in the vertically stacked configuration. This intermediate insulating layer prevents electrical interference and short circuits between the closely spaced gate structures, enabling higher integration density while maintaining reliable electrical insulation.
Solution Approach 2:
The patent transitions from planar transistor arrangements to vertically stacked three-dimensional structures, stacking multiple channel layers and gate structures in the vertical dimension. This dimensional change allows significantly higher integration density within the same footprint area while the gate isolation insulating layer ensures proper electrical separation in this new three-dimensional configuration.
2Volume of moving object
If gate structures are placed adjacent to each other in vertical stacking, then device compactness improves, but electrical interference between gates increases
Solution Approach 1:
The gate isolation insulating layer serves as a mediating structure positioned between adjacent gate structures in the vertical stack. This intermediate layer blocks electrical interference and crosstalk between the first gate structure and second gate structure, allowing them to be placed in close proximity for compact device design while eliminating harmful electrical interactions.
3Reliability
If middle dielectric isolation structures are used between channel layers, then electrical insulation is improved, but manufacturing process complexity increases
Solution Approach 1:
The middle dielectric isolation structure and gate isolation insulating layer are combined into a unified insulating system. The gate isolation insulating layer is integrated with the existing dielectric isolation structures between channel layers, creating a comprehensive electrical insulation architecture that maintains high reliability while avoiding the need for entirely separate manufacturing processes for each isolation function.
Data Source
AI summary
A semiconductor device includes a substrate, lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in the first direction, upper channel layers on the lower channel layers, respectively, and spaced apart from each other in the vertical direction, a middle dielectric isolation structure between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers, a lower gate structure on the lower channel layers; an upper gate structure on the upper channel layers on the lower gate structure and extending in a second direction perpendicular to the first direction. a gate isolation insulating layer between the lower gate structure and the upper gate structure, in contact with a side surface of the middle dielectric isolation structure, and extending around the lower gate structure.