Stacked Channel Gate Structure for Leakage and Resistance Control
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Solution Overview
Problem
Semiconductor devices face challenges in reducing leakage current and improving channel resistance while maintaining uniform work function and high doping concentration, which affects their performance and reliability.
Innovation Solution
The semiconductor device design includes a channel pattern with stacked semiconductor patterns and a gate pattern featuring main and sub-gate portions, along with inner gate spacers, to optimize the distance and shape for improved epitaxial formation of source/drain patterns, reducing leakage current and enhancing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is shortened to improve switching speed, then the switching speed increases, but the leakage current increases
Solution Approach 1:
The gate electrode is divided into multiple gate portions (first gate portion, second gate portion, third gate portion) positioned at different heights. This segmentation allows each gate portion to control different regions of the channel independently, enabling effective suppression of leakage current even in short-channel devices while maintaining high switching speed.
Solution Approach 2:
The patent introduces a vertical dimension by stacking gate portions at different heights above the channel. This three-dimensional gate structure provides enhanced control over the channel, allowing simultaneous optimization of switching speed and leakage current suppression that cannot be achieved with conventional planar gates.
2Reliability
If the doping concentration is increased to improve channel resistance, then the channel resistance decreases, but the work function uniformity deteriorates
Solution Approach 1:
Different gate portions are positioned to control different regions of the channel with locally optimized doping concentrations. The first gate portion controls a first region, the second gate portion controls a second region, and the third gate portion controls a third region, each with tailored doping to achieve uniform work function while maintaining low channel resistance.
Solution Approach 2:
The patent employs different doping concentrations in different channel regions corresponding to different gate portions. By adjusting doping parameters (concentration, depth, distribution) for each region, the work function uniformity is maintained while achieving the required channel resistance characteristics.
3Productivity
If the source/drain spacing is reduced to improve device integration, then the device density increases, but the epitaxial formation uniformity deteriorates
Solution Approach 1:
The gate portions are positioned and configured before the epitaxial formation of source/drain structures. This preliminary configuration of the multi-level gate structure establishes proper spacing and alignment that guides uniform epitaxial growth, enabling high device density while maintaining epitaxial formation uniformity.
Data Source
AI summary
A semiconductor device is provided including an active pattern disposed on a substrate, a source/drain pattern on the active pattern, a channel pattern configured to electrically connect the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a gate pattern configured to cross between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and to have a main gate portion and sub-gate portions, and inner gate spacers between the sub-gate portions and the source/drain pattern. A first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between adjacent source/drain patterns passing through the semiconductor patterns in the second direction.