Stacked Channel Gate Structure for Low-Capacitance MOSFET Scaling
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Solution Overview
Problem
As semiconductor devices scale down, the operating characteristics of MOSFETs deteriorate, leading to challenges in achieving superior performance and high integration without compromising electrical characteristics.
Innovation Solution
The semiconductor device includes an active pattern on a substrate, source/drain patterns, a channel pattern with semiconductor patterns in a vertical stack, and a gate electrode with varying width sections that adapt to the depth of the channel pattern, reducing parasitic capacitance by omitting inner spacers between the gate electrode and source/drain patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is scaled down to increase integration density, then device integration is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to 3D vertical stacked channel structure. Multiple semiconductor patterns are stacked vertically to form multi-layer channels, enabling increased integration density while maintaining effective channel width and electrical performance. The gate electrode wraps around the vertical channel structure, providing three-dimensional gate control that preserves operating characteristics despite scaling.
Solution Approach 2:
The channel region is segmented into multiple discrete semiconductor patterns stacked vertically, with gate electrode parts positioned between each stack. This segmentation allows independent optimization of each channel layer and enables higher integration through increased vertical stacking without compromising individual channel performance.
2Stability of the object's composition
If inner spacers are included between gate electrode and source/drain patterns, then structural stability is improved, but parasitic capacitance increases
Solution Approach 1:
The patent removes the inner spacer component from the conventional structure. By eliminating the dielectric material between the gate electrode and source/drain patterns, parasitic capacitance is reduced. Structural stability is maintained through alternative design features such as precise positioning of the gate electrode parts and optimization of the semiconductor pattern geometry.
Solution Approach 2:
The patent converts the potential harm of direct contact between gate electrode and source/drain into a benefit by reducing parasitic capacitance. The close proximity or direct contact that would normally increase capacitance is instead used to reduce the need for additional spacer structures, simplifying the device architecture while improving electrical performance.
Data Source
AI summary
A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.