Stacked Channel Gate Structure With Inner Spacer for Capacitance Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high performance and reliability due to increased integration demands, particularly in reducing capacitance between the gate electrode and source/drain patterns and preventing diffusion of materials into channel patterns.
Innovation Solution
The semiconductor device incorporates a design with an inner gate spacer between the gate electrode and source/drain pattern, and an insulating film structure between the gate electrode and channel patterns, using high dielectric constant materials to reduce capacitance and prevent material diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode is positioned close to the source/drain pattern to improve device integration, then the device density increases, but the capacitance between gate electrode and source/drain pattern increases causing performance degradation
Solution Approach 1:
An inner gate spacer is introduced as an intermediary structure between the gate electrode and the source/drain pattern. This spacer reduces the capacitance between these components while allowing them to remain in close proximity for high integration, thus resolving the contradiction between device density and capacitance control.
2Productivity
If the gate electrode is positioned close to the channel pattern to improve device integration, then the device density increases, but material diffusion into the channel pattern occurs causing reliability issues
Solution Approach 1:
An insulating film structure is introduced as an intermediary between the gate electrode and the channel pattern. This film prevents material diffusion from the gate electrode into the channel pattern while allowing the components to remain in close proximity, thus resolving the contradiction between device integration and material diffusion prevention.
3Ease of manufacture
If the device structure is simplified to reduce manufacturing complexity, then the ease of manufacture improves, but the ability to control capacitance and prevent material diffusion deteriorates
Solution Approach 1:
The gate electrode structure is segmented into multiple components including the inner gate spacer and insulating film structure. This segmentation allows for precise control of capacitance and material diffusion while maintaining manufacturability through standardized fabrication processes.
Solution Approach 2:
The inner gate spacer and insulating film structure serve as intermediary elements that provide precise control over capacitance and material diffusion. These additional structures, while increasing complexity, enable reliable device operation through controlled interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves semiconductor performance by reducing capacitance and enhances reliability by minimizing material diffusion, thereby supporting higher integration and functionality.
Implementation Method 1
a high dielectric constant insulating film on the interfacial insulating film
Implementation Method 2
an insulating film structure between the gate electrode and the plurality of channel patterns... preventing or reducing in likelihood the constituent material of the inner gate spacer from diffusing into the channel pattern
Data Source
AI summary
A semiconductor device comprising, a substrate, an active pattern on the substrate, the active pattern including a plurality of channel patterns spaced apart from each other and vertically stacked on each other, a source/drain pattern on at least one side of the plurality of channel patterns, a gate electrode surrounding the plurality of channel patterns, the gate electrode including a lower gate electrode between adjacent channel patterns of the plurality of channel patterns, an insulating film structure between the gate electrode and the plurality of channel patterns, and an inner gate spacer between the source/drain pattern and the lower gate electrode, wherein a sidewall of the insulating film structure is between the source/drain pattern and the inner gate spacer.