Stacked Channel-Layer Gate Structure for Sub-Threshold Leakage Control
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Solution Overview
Problem
Semiconductor devices with high integration face challenges in reducing sub-threshold leakage current and enhancing operating threshold voltage distribution due to the miniaturization of transistors with three-dimensional channel structures.
Innovation Solution
A semiconductor device with vertically spaced channel layers, including a gate structure that varies in work function across different electrode portions to prevent parasitic threshold voltage formation, thereby reducing sub-threshold leakage current and enhancing operating threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors with three-dimensional channel structures are miniaturized to increase integration, then device integration is improved, but sub-threshold leakage current increases
Solution Approach 1:
The channel is segmented into multiple vertically spaced channel layers (first channel layer, second channel layer, third channel layer) separated by isolation regions. This segmentation allows the gate structure to independently control each layer, preventing sub-threshold leakage while maintaining high integration through vertical stacking.
Solution Approach 2:
The gate structure has different work functions at different vertical levels: the first gate electrode portion has a first work function and the second gate electrode portion has a second work function. This local quality variation allows precise control of threshold voltages in different channel layers to eliminate sub-threshold leakage.
2Productivity
If transistors with three-dimensional channel structures are miniaturized to increase integration, then device integration is improved, but operating threshold voltage distribution deteriorates
Solution Approach 1:
The gate structure is segmented into multiple electrode portions (first gate electrode portion, second gate electrode portion, third gate electrode portion) at different vertical levels, each independently controllable. This segmentation enables precise adjustment of threshold voltage distribution across the three-dimensional channel structure.
Solution Approach 2:
Different gate electrode portions are assigned different work functions to locally adjust threshold voltages in specific channel layers. The first gate electrode portion has a first work function while the second gate electrode portion has a second work function, enabling optimized threshold voltage distribution for reliable operation.
3Productivity
If channel layers are vertically stacked to achieve high integration, then device integration is improved, but sub-threshold leakage current increases
Solution Approach 1:
The vertically stacked channel structure is segmented into discrete channel layers separated by isolation regions. Each channel layer can be independently controlled by corresponding gate electrode portions, preventing sub-threshold leakage current while maintaining high vertical integration.
Solution Approach 2:
Isolation regions are introduced as intermediary structures between adjacent channel layers. These isolation regions act as barriers that prevent unwanted electrical coupling and sub-threshold leakage between channel layers while allowing the gate structure to maintain control over each layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces sub-threshold leakage current and enhances electrical performance by maintaining a higher parasitic threshold voltage than operating threshold voltage, ensuring efficient operation of transistors.
Implementation Method 1
a first gate electrode in contact with the first gate dielectric. The first gate electrode includes a first lower electrode portion between the first active fin and the first lower channel layer, a first intermediate electrode portion between the first lower channel layer and the first intermediate channel layer, and a first upper electrode portion between the first intermediate channel layer and the first upper channel layer
Data Source
AI summary
A semiconductor device includes a substrate, an active fin on the substrate, and a transistor on the active fin. The transistor includes a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially stacked, and a gate structure traversing the active fin, respectively surrounding the channel layers, and including a gate dielectric and a gate electrode. The gate electrode includes a lower electrode portion between the active fin and the lower channel layer, an intermediate electrode portion between the lower channel layer and the intermediate channel layer, and an upper electrode portion between the intermediate channel layer and the upper channel layer. The gate electrode includes a work function adjusting metal element, and a content of the work function adjusting metal element in the lower electrode portion is different from that in each of the intermediate electrode portion and the upper electrode portion.