Stacked Channel Semiconductor Structure for Leakage Control
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to increased integration, leading to challenges in achieving superior performance and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with vertically stacked semiconductor patterns, a gate electrode with inner electrodes, and an insulation pattern including a dielectric and protection layer to enhance electrical properties and reliability, while preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density improves, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D MOSFET structures to three-dimensional vertically stacked semiconductor patterns, enabling multiple active channels to be stacked vertically. This dimensional change allows increased device density without further lateral scaling, thereby maintaining operating characteristics while improving integration density.
Solution Approach 2:
The channel region is segmented into multiple discrete semiconductor patterns stacked vertically, with each pattern forming a separate active channel. This segmentation allows independent control and optimization of each channel's electrical properties, improving overall device performance while achieving high integration.
2Reliability
If vertically stacked semiconductor patterns are implemented, then device performance improves, but leakage current increases
Solution Approach 1:
An insulation pattern is introduced as an intermediary layer between the vertically stacked semiconductor patterns and the substrate. This intermediate insulation layer effectively blocks leakage current paths while maintaining the electrical integrity of the vertical channels, thus suppressing harmful leakage without compromising device performance.
Solution Approach 2:
The harmful leakage current paths are extracted and isolated by introducing separate insulation regions between the vertical channels and the substrate. This extraction of leakage paths allows the vertical stacked structure to maintain its performance benefits while eliminating the harmful electrical leakage.
3Reliability
If complex gate electrode structures with inner electrodes are used, then electrical control improves, but manufacturing complexity increases
Solution Approach 1:
The gate electrode structure employs nested inner electrodes positioned within recesses of the vertical stacked semiconductor patterns. This nesting arrangement allows the gate to effectively control multiple channels from a compact structure, improving electrical control while managing manufacturing complexity through systematic patterning.
Data Source
AI summary
A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.