Stacked Transistor Channel Memory Structure for Higher Cell Density
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving increased memory cell density, reduced footprint, and efficient integration of memory structures with logic structures, leading to limitations in processing speed and manufacturing costs.
Innovation Solution
The semiconductor device incorporates a memory structure with vertically stacked layers of memory cells and shared vias among multiple gate structures, allowing for increased memory cell density and integration with logic structures, enabling in-memory computing and reduced manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar memory structures are used, then manufacturing processes are simpler, but memory cell density and device footprint are limited
Solution Approach 1:
The patent implements vertically stacked memory cell layers above the logic structure, transitioning from planar to three-dimensional architecture. This stacking approach increases memory cell density by utilizing the vertical dimension while maintaining compatibility with existing manufacturing processes through sequential formation steps.
Solution Approach 2:
The memory structure is nested above the logic structure, with memory cell layers stacked vertically over the logic circuitry. This nesting arrangement allows memory and logic to share the same footprint area, effectively increasing memory cell density without proportionally increasing device area.
2Area of stationary object
If memory structure and logic structure are separated, then functionality is clearer, but device footprint and integration complexity increase
Solution Approach 1:
The patent places the memory structure in the vertical dimension above the logic structure, rather than lateral integration. This vertical separation maintains clear functional boundaries between memory and logic while reducing the horizontal footprint, as memory cells stack upward instead of extending outward.
Solution Approach 2:
The device is segmented into distinct logic and memory portions, with the memory structure formed as a separate stacked assembly above the logic structure. This segmentation allows independent optimization of each function while reducing overall footprint through vertical stacking.
3Quantity of substance
If more memory cells are integrated, then memory capacity increases, but processing speed and access time may be compromised
Solution Approach 1:
The memory array is segmented into multiple stacked layers, each accessible through dedicated word lines and bit lines. This segmentation allows parallel access to different memory layers, maintaining processing speed while increasing total memory capacity through vertical stacking.
Solution Approach 2:
Memory cells are arranged in vertical stacks with each layer accessible independently through through-silicon vias and interconnect structures. This three-dimensional arrangement enables simultaneous access to multiple layers, preserving processing speed while scaling memory capacity vertically.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a memory structure including a first transistor channel, a gate structure overlying the first transistor channel, and a second transistor channel overlying the gate structure. The gate structure includes a control gate.