Stacked Semiconductor Channel Layout for Lower-Transistor Plug Access
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Solution Overview
Problem
In semiconductor manufacturing, particularly for vertically stacked complementary FETs, it is challenging to efficiently lead out electricity from lower-layer transistors due to the overlapping structure of channel and gate layers, which hinders the formation of source-drain and gate plugs.
Innovation Solution
The semiconductor structure is designed with non-orthogonal projections of the second channel layer and first channel layer onto the substrate, allowing for reduced blocking of the forming process of source-drain and gate plugs, enabling easier electricity extraction while maintaining electrical isolation between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked complementary FET structure is adopted to improve integration density, then transistor integration density is improved, but electricity extraction from lower-layer transistors becomes difficult
Solution Approach 1:
The patent employs asymmetric angular orientation between the first device channel layer structure and the second device channel layer structure. Specifically, the first channel layer structure extends in a first angular direction while the second channel layer structure extends in a second angular direction, creating a non-overlapping geometric configuration. This asymmetric angular arrangement allows source-drain and gate plugs to be formed without being blocked by the other device's channel structure, thereby enabling electricity extraction from both stacked transistors while maintaining high integration density.
2Ease of manufacture
If non-orthogonal projection configuration is used to facilitate plug formation, then ease of manufacture is improved, but device area increases
Solution Approach 1:
The patent resolves the area increase issue by utilizing angular orientation in the planar dimension rather than increasing vertical stacking height or lateral separation. By orienting the first and second channel layer structures at different angles within the same substrate plane, the design enables plug formation without blocking while maintaining compact footprint. This dimensional approach allows electricity extraction pathways to diverge angularly rather than requiring additional vertical or lateral space.
Data Source
AI summary
A semiconductor structure and a forming method thereof are provided. One form of a semiconductor structure includes: a first device structure, including a first substrate and a first device formed on the first substrate, the first device including a first channel layer structure located on the first substrate, a first device gate structure extending across the first channel layer structure, and a first source-drain doping region located in the first channel layer structure on two sides of the first device gate structure; and a second device structure, located on a front surface of the first device structure, including a second substrate located on the first device structure and a second device formed on the second substrate, the second device including a second channel layer structure located on the second substrate, a second device gate structure extending across the second channel layer structure, and a second source-drain doping region located in the second channel layer structure on two sides of the second device gate structure, where projections of the second channel layer structure and the first channel layer structure onto the first substrate intersect non-orthogonally. The electricity of the first device can be led out according to the present disclosure.