Tunable Stacked Channel Transistors With Source/Drain Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving tunable numbers of stacked semiconductor channel layers in multi-gate transistors for different regions of an IC chip to meet varying current driving requirements, while also suppressing substrate leakage current.
Innovation Solution
The method involves forming epitaxial source/drain features with an insulation layer that isolates the base epitaxial layer from contacting the substrate, allowing for adjustable channel layers by controlling the number of functional layers in different regions, and using a cyclic deposition process to form the insulation layer and air gaps, which reduces leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of stacked channel layers is increased to improve current driving capability, then high-performance computing regions achieve higher operating speed, but substrate leakage current increases
Solution Approach 1:
The substrate is divided into multiple isolation regions with different numbers of stacked channel layers. Each isolation region can be independently configured to have a specific number of channel layers (e.g., 3, 5, or 7 layers) based on the performance requirements of different functional blocks, allowing high-performance regions to have more layers while low-power regions have fewer layers, thus reducing overall substrate leakage.
Solution Approach 2:
Different regions of the substrate are assigned different channel layer configurations tailored to their specific functional requirements. High-performance computing regions use configurations with more channel layers for higher current driving capability, while I/O and low-power regions use configurations with fewer channel layers to minimize leakage, achieving local optimization of both performance and power efficiency.
2Reliability
If different transistor constructions are used for different functions to meet specific performance requirements, then current driving capability and leakage performance are optimized, but manufacturing process complexity increases
Solution Approach 1:
A single unified manufacturing process is developed that can fabricate multiple transistor variants with different numbers of stacked channel layers using the same process steps. The process uses common materials, deposition techniques, and patterning methods, allowing the same fabrication line to produce transistors with 3, 5, or 7 channel layers without requiring separate production lines or significantly different process configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of multi-gate transistors with tunable channel layers, meeting diverse current driving needs and significantly reducing substrate leakage current, thereby enhancing the performance and efficiency of IC chip regions.
Implementation Method 1
forming an insulation layer in the source/drain recess, wherein the insulation layer isolates the base epitaxial layer from contacting the substrate
Implementation Method 2
using a cyclic deposition process to form the insulation layer and air gaps
Data Source
AI summary
A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.