Stacked Channel Layout With Separation Patterns for Low-Resistance Integration
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Solution Overview
Problem
The increasing degree of integration in semiconductor devices leads to degraded operating properties, necessitating the development of high-performance semiconductor devices with improved electrical properties.
Innovation Solution
A semiconductor device design featuring first and second cells in rows with a merged cell, utilizing separation patterns and structures to enhance channel patterns and gate structures, allowing for increased integration and improved electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased, then more functions and higher performance can be achieved, but operating properties are lowered or degraded
Solution Approach 1:
The semiconductor device is divided into multiple cells (first cell, second cell, merged cell) with distinct separation patterns and separation structures. Each cell contains independently formed channel patterns, gate structures, and source/drain patterns, allowing individual optimization while achieving high integration through systematic arrangement.
Solution Approach 2:
Different regions of the semiconductor device are given different structural characteristics. The merged cell has a wider active pattern width compared to individual cells, and separation structures are strategically positioned to provide electrical isolation where needed while maintaining continuity in other regions. This local differentiation optimizes electrical properties in specific areas.
2Productivity
If channel patterns are separated into multiple regions, then device integration is enhanced, but resistance may increase
Solution Approach 1:
Adjacent channel patterns from different cells are merged into continuous channel regions. The first channel patterns and second channel patterns are formed to be adjacent to each other, creating extended conductive paths that reduce resistance while maintaining the integrated cell structure.
Solution Approach 2:
The channel patterns are designed to provide continuous conductive paths through the device. By ensuring that channel patterns from different cells are adjacent and properly connected, the invention maintains continuous electrical action across cell boundaries, preventing resistance accumulation at interfaces.
3Reliability
If gate structures are separated by separation patterns, then cell isolation is improved, but gate structure continuity may be disrupted
Solution Approach 1:
Separation patterns are introduced between cells to provide electrical isolation. These separation patterns create distinct regions for different cells while allowing the overall gate structure to maintain its functional integrity through careful design of the separation pattern geometry and positioning.
Data Source
AI summary
A semiconductor device includes an active pattern extending on a substrate in a first direction, channel patterns vertically stacked on the active pattern, a separation structure extending in a second direction and separating each of the active pattern and the channel patterns into first and second portions, a gate structure extending in the second direction and onto the first portions of the channel patterns, a separation pattern extending in the first direction, separating the first portions of the channel patterns into first and second channel patterns, and separating the gate structure into first and second gate structures, and a third gate structure extending in the second direction and onto the second portions of the channel patterns. The second portions of the channel patterns have a width greater than a sum of first and second widths of the first and second channel patterns, respectively.