Stacked Channel Semiconductor Structure for Source/Drain Isolation
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in improving the integration and electrical characteristics of metal oxide semiconductor FETs, particularly due to size reduction limitations, necessitating the development of advanced transistor structures like gate-all-around type field effect transistors and finFETs with nanosheets surrounded by gates.
Innovation Solution
A semiconductor device design featuring active patterns on a substrate with stacked channel layers, isolation and interlayer insulating structures, and gate structures that provide improved electrical isolation and reliability through a specific configuration of source/drain patterns and insulating layers, including a topological selective film for stable separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of metal oxide semiconductor FETs is reduced to increase integration, then the degree of integration is improved, but the electrical characteristics deteriorate due to size reduction limitations
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional stacked channel layers (first and second channel layers vertically stacked), enabling increased integration density while maintaining effective channel width and electrical characteristics through vertical dimension exploitation
Solution Approach 2:
The gate structure completely surrounds each channel layer in a gate-all-around configuration, with the gate electrode wrapping around the channel layer from all sides, providing maximum gate control over the current flow while maintaining compact structure for high integration
2Device complexity
If traditional planar MOSFET structure is used, then the structure is simple, but the electrical characteristics and speed performance are limited
Solution Approach 1:
The patent employs vertically stacked channel layers with gate-all-around structures, transitioning from planar to three-dimensional architecture to achieve superior gate control and electrical characteristics while maintaining manufacturing feasibility
Solution Approach 2:
The channel region is divided into multiple discrete stacked layers (first and second channel layers) separated by intermediate insulating patterns, allowing independent optimization of each layer's electrical characteristics and improved overall device performance
3Productivity
If source/drain patterns are closely spaced to increase integration, then the degree of integration is improved, but electrical isolation between patterns becomes insufficient
Solution Approach 1:
The patent introduces an isolation insulating layer positioned between the first and second source/drain patterns, serving as an intermediary element that provides effective electrical isolation while enabling closer pattern spacing and higher integration density
Solution Approach 2:
The isolation insulating layer extends in the vertical direction with varying thickness (thinner at edge portions, thicker at central portion), utilizing the vertical dimension to achieve isolation without increasing horizontal footprint, thus maintaining high integration
Data Source
AI summary
A semiconductor device includes an active pattern extending on a substrate in a first direction; first and second lower channel layers in a first region and a second region of the active pattern, respectively; first and second upper channel layers on the first and second lower channel layers, respectively; a first source/drain pattern connected to the first and second lower channel layers; an isolation insulating layer on surfaces of the first source/drain pattern in the second direction, where a thickness of opposing edge portions of the isolation insulating layer when viewed in cross section along the first direction is smaller than a thickness of a central portion therebetween; a second source/drain pattern connected to the first and second upper channel layers; and an interlayer insulating layer on the second source/drain patterns and on the isolation insulating layer.