Stacked Channel Transistors for Integration Density and Electrical Variation
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Solution Overview
Problem
Highly integrated semiconductor devices require improved transistor designs to achieve distinct electrical characteristics without increasing device size or complexity, as existing transistors have limitations in varying electrical performance due to shared impurity regions and channel pattern configurations.
Innovation Solution
The semiconductor device incorporates multiple epitaxial patterns and channel patterns with varying numbers and thicknesses, along with distinct gate structures, to create transistors with different electrical characteristics, allowing for higher operating currents and integration without additional isolation patterns or space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transistors share common impurity regions and channel patterns, then device integration is improved, but electrical characteristic differentiation deteriorates
Solution Approach 1:
The patent applies local quality by creating different transistor characteristics through localized structural variations. Specifically, first and second transistors are formed with different numbers of channel patterns (first channel patterns vs. second channel patterns) while sharing common source and drain regions. This local differentiation in channel pattern quantity enables distinct electrical characteristics (different operating currents) without requiring separate impurity regions, thus resolving the contradiction between integration density and electrical characteristic variation.
Solution Approach 2:
The patent implements universality by having multiple transistors share common impurity regions (source and drain regions) and epitaxial structures. The first and second transistors both utilize the same first and second epitaxial patterns as their source/drain regions, allowing these regions to serve multiple functions for different transistors. This multi-functionality approach increases integration density while the electrical characteristics are differentiated through the number of channel patterns rather than through separate impurity regions.
2Power
If transistor size is increased to improve electrical performance, then operating current is improved, but device area increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar transistor designs to vertically stacked channel patterns. Multiple channel patterns are stacked in the vertical direction (third direction perpendicular to substrate) between the source and drain regions. This vertical stacking enables increased operating current through multiple parallel conduction paths without increasing the lateral footprint of the device, thus resolving the contradiction between operating current and device area.
Solution Approach 2:
The patent implements nesting by placing multiple channel patterns within the vertical space between the source and drain regions. The first and second channel patterns are nested vertically, with each channel pattern containing multiple stacked channels. This nested arrangement allows multiple current-carrying paths to occupy the same lateral space, increasing power handling capability without proportionally increasing device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the formation of transistors with distinct electrical characteristics in a compact layout, enhancing integration density and performance by varying channel pattern numbers and thicknesses, thus improving operational currents without altering the effective area or requiring additional isolation.
Implementation Method 1
a first active structure on a substrate and including a first epitaxial pattern, a second epitaxial pattern
Data Source
AI summary
A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.