Stacked Channel Memory Structure With Central Wiring Bonding
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density and efficient data processing due to limitations in bonding methods and structural design, which affect their capacity and reliability.
Innovation Solution
The semiconductor device incorporates a stacked structure with a source conductive layer connecting channel structures between memory cell regions, enhancing integration density by sharing common wiring layers and bit lines, and utilizing a bonding method between semiconductor structures to increase packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafer bonding method is used to bond semiconductor structures, then integration density is improved, but bonding reliability and electrical connection stability may deteriorate
Solution Approach 1:
The patent divides the bonding interface into multiple discrete bonding regions distributed across the wafer surface, rather than relying on a single large bonding area. This segmentation allows for localized bonding verification and reduces the impact of defects in any single region, thereby improving overall bonding reliability while maintaining high integration density through multiple stacked memory cell layers.
Solution Approach 2:
The patent introduces an intermediary bonding layer or transition structure between the stacked semiconductor wafers that facilitates reliable electrical and mechanical connections. This intermediary structure acts as a mediator that ensures stable electrical connections between channel structures across bonded interfaces, resolving the reliability issue while preserving the high integration density achieved through wafer bonding.
2Quantity of substance
If stacked memory cell structures are implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs universal bonding interfaces and standardized connection structures that can be repeatedly applied across multiple stacked layers. The same bonding pattern and electrical connection topology are used throughout the stacked memory cell structures, which simplifies the manufacturing process despite the increased number of layers, thereby reducing overall device complexity while maintaining high integration density.
Solution Approach 2:
The patent implements a nested structure where simpler repeating units (individual memory cell layers with standardized bonding interfaces) are stacked to form the complete high-density device. Each layer is a self-contained unit that can be manufactured independently and then bonded together, which reduces the complexity of the overall manufacturing process while achieving high integration density through vertical stacking.
3Reliability
If channel structures are connected between memory cell regions, then electrical connection stability is improved, but device complexity increases
Solution Approach 1:
The patent merges the channel structures from adjacent memory cell regions into a shared common channel that serves multiple memory cell arrays. This consolidation reduces the total number of separate wiring connections needed while maintaining stable electrical connections across all memory regions, thereby reducing device complexity while improving electrical connection stability through shared infrastructure.
Data Source
AI summary
A semiconductor device includes first gate electrodes, a first channel structure penetrating the first gate electrodes and including a first channel layer and a first channel filling insulating layer, second gate electrodes above the first gate electrodes, a second channel structure penetrating the second gate electrodes and including a second channel layer and a second channel filling insulating layer, and a central wiring layer between the first gate electrodes and the second gate electrodes and connected to the first channel layer and the second channel layer, wherein the first channel layer and the second channel layer are connected to each other in a region surrounded by the central wiring layer, and the first channel filling insulating layer and the second channel filling insulating layer are connected to each other in a region surrounded by the central wiring layer.