Stacked Semiconductor Channels With Buffer Layer for Leakage Control
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Solution Overview
Problem
At technology nodes below 5 nm, MOS field-effect transistor devices face challenges such as source-drain punch-through, short-channel effects, and increased leakage current due to the difficulty in fabricating ultra-steep PN junctions, leading to degraded gate control and higher power consumption.
Innovation Solution
A semiconductor structure with vertically stacked N-type and P-type conductive channel layers, including doped regions and a conductive buffer layer to reduce electrical interference, along with a gate structure that surrounds the channels, enhancing device integration and drive current while minimizing horizontal area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is shrunk to improve device scaling, then the drive current is improved, but the gate control ability deteriorates and leakage current increases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel structures. Multiple channel layers are stacked in the vertical direction, allowing the channel length to be extended vertically while maintaining compact horizontal footprint. This dimensional change enables better gate control over the channels while preserving drive current at scaled dimensions.
Solution Approach 2:
The gate structure completely surrounds each channel layer in a nested configuration, with the gate wrapping around the channel from all sides. This nested arrangement provides 360-degree gate control over the channel, significantly improving electrostatic control and reducing short-channel effects while maintaining effective drive current.
2Reliability
If ultra-steep PN junctions are fabricated to improve device performance, then the gate control is improved, but the manufacturing difficulty increases
Solution Approach 1:
The device is segmented into multiple discrete channel layers stacked vertically, with independent doping regions for each layer. This segmentation allows each layer to be formed and doped separately using standard fabrication processes, avoiding the need to create extremely steep doping gradients in a single continuous junction while achieving similar electrostatic control benefits.
3Area of stationary object
If vertically stacked channel layers are used to improve integration, then the chip area is saved, but the electrical interference between doped regions increases
Solution Approach 1:
Conductive buffer layers are inserted between adjacent doped regions in the vertically stacked structure. These buffer layers act as intermediaries that electrically isolate neighboring doped regions, preventing harmful electrical interference and crosstalk while maintaining the compact vertical integration and small chip area footprint.
Data Source
AI summary
A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.