Stacked Semiconductor Channels With Mixed Materials for Dense MOSFETs
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving superior performance due to the limitations of high integration, particularly in the scaling down of MOSFETs, which affects the operating characteristics and integration of field effect transistors.
Innovation Solution
The semiconductor device incorporates a substrate with multiple regions, each featuring distinct channel structures and gate electrodes, including vertically stacked channel patterns made of different semiconductor materials, with a third channel structure having an uneven sidewall covered by a gate dielectric layer, allowing for optimized transistor properties across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked channel patterns are formed to increase integration density, then the integration of field effect transistors is improved, but the manufacturing precision and control of channel structures become more difficult
Solution Approach 1:
The channel structure is segmented into multiple independent channel patterns (first, second, and third channel patterns) that are vertically stacked and separated by dielectric layers. This segmentation allows each channel pattern to be independently formed and controlled, enabling high integration density while maintaining manufacturing precision through separate processing steps for each channel layer.
Solution Approach 2:
The patent transitions from planar channel structures to three-dimensional vertically stacked channel patterns. By arranging channel patterns in the vertical dimension rather than only in the planar direction, the integration density is significantly increased while each individual channel pattern can still be manufactured with precise control using standard semiconductor fabrication techniques.
2Reliability
If different semiconductor materials are used in stacked channel patterns to optimize transistor properties, then the performance of field effect transistors is improved, but the device complexity increases
Solution Approach 1:
Different semiconductor materials are assigned to different channel patterns based on their specific functional requirements. The first channel pattern uses a first semiconductor material optimized for certain transistor characteristics, while the third channel pattern uses a second semiconductor material with different properties. This local optimization of material selection in different regions of the stacked structure enhances overall transistor performance while managing complexity through targeted material differentiation.
3Reliability
If gate dielectric layers are formed to cover uneven sidewalls of stacked channel structures, then the reliability of gate-channel interface is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate dielectric layer is formed preliminary to the gate electrode, creating a conformal coverage on the uneven sidewalls of the stacked channel structures before the gate electrode is deposited. This preliminary formation of the dielectric layer ensures complete coverage of the irregular surfaces, improving the reliability of the gate-channel interface while allowing subsequent gate electrode formation to proceed with standard precision requirements.
Data Source
AI summary
A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.