Vertically-Stacked Charge-Trapping Zones for NAND Flash
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory technologies face challenges in achieving large memory windows, good charge retention, and uniformity across NAND arrays due to parasitic capacitive coupling and stress-induced gate leakage, particularly when transitioning to multilevel cells.
Innovation Solution
The implementation of vertically-stacked charge-trapping zones with metallic charge-trapping materials, such as nanoparticles, and high-k dielectric materials to enhance charge trapping and retention, allowing for independent programming of each zone to achieve multiple memory states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge-trapping materials are used in non-volatile memory cells, then charge retention is improved, but obtaining large memory windows and uniformity across NAND arrays becomes difficult
Solution Approach 1:
The patent divides the charge-trapping functionality into multiple discrete metallic charge-trap layers (first charge-trap layer, second charge-trap layer, third charge-trap layer) separated by dielectric layers. This segmentation allows each layer to contribute independently to charge retention while reducing variability, as the overall charge storage is distributed across multiple uniform layers rather than relying on a single non-uniform layer.
Solution Approach 2:
The patent employs composite structures combining metallic charge-trap materials (such as aluminum, copper, or their alloys) with high-k dielectric materials. This composite approach leverages the high charge retention of metals while the dielectric layers provide electrical isolation and structural uniformity, achieving both good charge retention and manufacturing precision.
2Loss of information
If floating gate is charged to store data, then memory states are achieved, but parasitic capacitive coupling effects and stress-induced gate leakage occur
Solution Approach 1:
The patent extracts the charge-trapping function from the traditional floating gate structure and implements it through separate metallic charge-trap layers embedded within dielectric layers. This separation removes the harmful parasitic coupling and stress-induced leakage effects associated with conventional floating gates while preserving the data storage capability through controlled charge injection into the metallic traps.
Solution Approach 2:
The dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) act as intermediaries between the metallic charge-trap layers and the control gate. These intermediary layers provide electrical isolation that eliminates parasitic capacitive coupling while allowing controlled charge transfer during programming operations, thus preventing harmful side effects.
3Measurement precision
If memory window is increased to enable clear separation of MLC states, then multiple memory states can be distinguished, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent segments the charge-trapping function into multiple discrete metallic layers, where each layer can be independently controlled to represent different memory states. This segmentation naturally creates distinct charge levels (0, 1, 2, 3 electrons) that correspond to MLC states, achieving clear state separation through the physical structure rather than complex control mechanisms.
Solution Approach 2:
The patent utilizes changes in the number of trapped electrons (charge quantity parameter) in the metallic charge-trap layers to encode multiple memory states. By controlling the charge injection process to add discrete numbers of electrons to the metallic traps, the patent achieves multiple distinguishable memory states (0-3 electrons) with a relatively simple layered structure, avoiding the need for complex device architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the memory window and charge retention capacity, reduces cell-to-cell sigma variation, and enables scalable NAND flash beyond the 50 nanometer node by improving the probability of charge capture and reducing electric field stress.
Implementation Method 1
Each of the charge-trapping zones may comprise a plurality of discrete islands of charge-trapping material... The individual charge-trapping zones may be programmed independently of one another
Implementation Method 2
The gate stack may comprise... high-k dielectric material... increases the memory window and charge retention capacity, reduces cell-to-cell sigma variation
Data Source
AI summary
Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.