Stacked Chip Address Decoding Through TSV Logic Circuits
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Solution Overview
Problem
The challenge in vertically stacked semiconductor chips is selecting and decoding individual chips efficiently due to identical terminal connections, which complicates the selection process.
Innovation Solution
The use of through silicon vias (TSVs) for signal transmission between stacked chips, combined with inverter and XOR circuits in each chip, allows for decoding and selecting arbitrary chips through logical operations, simplifying the selection process and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chips are vertically stacked with identical terminal connections, then chip density and integration are improved, but chip selection and decoding become complex and difficult
Solution Approach 1:
The address signal is segmented into multiple bits that are distributed to different chips in the stack. Each chip has a unique segment of the address space, allowing individual identification and selection through logical operations on the address bits rather than requiring complex wiring changes for each chip.
Solution Approach 2:
The patent transitions from horizontal wire bonding connections to vertical through-silicon-via connections, adding a vertical dimension to the interconnect architecture. This enables multiple chips to be stacked with identical terminal positions, simplifying the physical connection while maintaining selection capability through logical operations in the vertical dimension.
2Ease of manufacture
If wire bonding is used to connect stacked chips, then manufacturing process is simplified, but chip selection requires complex wiring changes
Solution Approach 1:
The patent replaces mechanical wiring changes with logical operations. Instead of physically reconfiguring wires to select different chips, the system uses logical AND operations between address signal segments and chip-specific decode signals to electronically select the target chip, eliminating the need for complex mechanical wiring changes.
3Productivity
If through silicon vias are used for signal transmission, then chip interconnection is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses standardized via dimensions and positioning that create equipotential conditions for alignment. By establishing uniform via specifications across all chips in the stack, the system reduces the precision burden on individual alignment operations, as each via follows the same reference standards and tolerance specifications.
Data Source
AI summary
A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.