Stacked Integrated Circuit With Even–Odd Address Redundancy
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Solution Overview
Problem
Existing stacked integrated circuits face challenges in efficiently transmitting data and control signals between stacked chips due to limitations in addressing and redundancy mechanisms, leading to potential errors and inefficiencies.
Innovation Solution
The implementation of even and odd areas within chips, each with dedicated through vias and address selection circuits, allows for the generation of internal addresses and redundancy addresses, enhancing data transmission and error correction in stacked integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate even and odd areas with dedicated through vias and address selection circuits are implemented, then data transmission efficiency and error resilience are improved, but device complexity increases
Solution Approach 1:
The chip is divided into separate even and odd areas, each with dedicated through vias and address selection circuits. This segmentation allows independent data paths for even and odd addresses, improving transmission efficiency and error resilience by preventing interference between address types while managing complexity through modular organization.
Solution Approach 2:
Different regions of the chip (even area vs. odd area) are given specialized functions with dedicated resources. The even area handles even addresses through even through vias and even address selection circuits, while the odd area handles odd addresses separately. This local specialization optimizes each region for its specific purpose, enhancing overall system performance.
2Reliability
If separate channels for data and control signals are enabled through even and odd areas, then error resilience is improved, but manufacturing complexity increases
Solution Approach 1:
The chip structure is segmented into even and odd areas with separate through via channels. This segmentation creates independent data and control signal paths, improving error resilience by isolating potential failures to specific channels. The manufacturing complexity is managed through systematic replication of the segmented structure.
Solution Approach 2:
The address selection circuits act as intermediaries that route control signals and data through appropriate even or odd channels based on the address type. This intermediary function enables separate channels for data and control signals, improving error resilience while maintaining manageable manufacturing processes through standardized routing logic.
Data Source
AI summary
The present disclosure provides a chip including an even area including an even through via through which an even address is received and an even redundancy through via through which an even redundancy address is received, and an odd area including an odd through via through which an odd address is received and an odd redundancy through via through which an odd redundancy address is received. In the present disclosure, the even area may include an even address selection circuit configured to, based on a chip information signal, generate a selection even address and a selection even redundancy address from the even address, the even redundancy address, the odd address, and the odd redundancy address, and an even internal address generation circuit configured to, based on an even repair signal, generate an internal even address from the selection even address and the selection even redundancy address.