Stacked Semiconductor Chip Layout for Adhesive Flow Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in maintaining package reliability due to difficulties in adjusting adhesive layers between stacked semiconductor chips, which affects the bonding and connection efficiency.
Innovation Solution
The introduction of a semiconductor device design featuring a first semiconductor chip with a quadrangle shape and a dummy pattern on its surface, which includes a through electrode and connection pads, along with an adhesive layer that surrounds the connection pads and dummy patterns, allowing for controlled adhesive flow and improved bonding between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked semiconductor package structure is used to increase storage capacity, then storage capacity is improved, but adhesive adjustment between chips becomes difficult
Solution Approach 1:
The dummy pattern is formed on the semiconductor substrate before chip stacking, establishing predetermined adhesive flow barriers that guide subsequent adhesive application. This preliminary structure enables controlled adhesive distribution during the stacking process, making adhesive adjustment easier despite the complex multi-chip configuration
Solution Approach 2:
The dummy pattern acts as an intermediary element between the chip connection pad and the adhesive layer. It provides a controlled interface that mediates adhesive flow, allowing the adhesive to be properly distributed and contained while bonding multiple chips together in the stacked package
2Reliability
If chip stacking is implemented to improve package reliability, then package reliability is improved, but adhesive flow control becomes challenging
Solution Approach 1:
The dummy pattern segments the adhesive application area into controlled zones. By dividing the potential adhesive flow path into distinct regions separated by the dummy pattern structure, precise control over adhesive distribution is achieved, ensuring proper bonding without excessive adhesive spread in the stacked package configuration
Solution Approach 2:
The dummy pattern is prepared in advance on the semiconductor substrate, creating predetermined boundaries and flow paths for the adhesive. This preliminary preparation ensures that when adhesive is applied during chip stacking, it flows exactly where needed with high precision, maintaining reliable bonds between stacked chips
Data Source
AI summary
A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.