Stacked Semiconductor Chip Assembly for Precise Alignment
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently stacking and aligning multiple chips while maintaining electrical connections and structural integrity.
Innovation Solution
A method of stacking semiconductor chips in a shifted manner with die attach films and connection wires, followed by flip-chip mounting and encapsulation with a mold resin layer to ensure proper alignment and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked in a conventional manner, then the number of chips can be increased, but the alignment precision and electrical connectivity between chips deteriorate
Solution Approach 1:
The patent introduces intermediate structures (support chips and connection chips) that segment the stacking process into manageable stages. Each chip is bonded to a support chip first, then multiple support chips are interconnected through connection chips, enabling precise alignment at each stage rather than attempting to align all chips simultaneously.
Solution Approach 2:
Support chips and connection chips serve as intermediary elements that facilitate the bonding process. These intermediaries provide stable platforms for mounting active chips and enable electrical connections between stacked chips through conductive structures, resolving the alignment and connectivity issues.
2Quantity of substance
If multiple chips are stacked to increase capacity, then the functionality is enhanced, but the structural integrity and reliability deteriorate
Solution Approach 1:
The patent employs support chips with larger areas than the active chips they support. These oversized support structures act as cushioning elements that distribute mechanical stresses and provide structural stability, preventing stress concentration that could compromise the reliability of the stacked configuration.
Solution Approach 2:
The patent uses different material compositions for different functional layers: support chips provide mechanical strength, connection chips provide electrical conductivity through conductive bump electrodes, and active chips provide computational functionality. This composite approach optimizes each layer for its specific function while ensuring overall structural integrity.
3Ease of manufacture
If conventional chip stacking is used, then the device can be manufactured, but the electrical connectivity between chips is insufficient
Solution Approach 1:
The patent replaces conventional mechanical wire bonding with direct mechanical-electrical integration through bump electrodes. The connection chips feature conductive bump structures that form direct electrical contacts with pads on support chips, eliminating the need for separate wiring processes and improving both connectivity reliability and manufacturing efficiency.
Data Source
AI summary
A semiconductor device includes: a wiring substrate in which a wiring layer is provided; a first semiconductor chip that is provided above the wiring substrate and on a surface of which a first pad is formed, the surface being on a side closer to the wiring substrate; a second semiconductor chip that is provided on the first semiconductor chip through a first resin layer and on a surface of which a second pad is formed, the surface being on a side opposite the wiring substrate; a third semiconductor chip that is provided on the second semiconductor chip through a second resin layer and on a surface of which a third pad is formed, the surface being on the side closer to the wiring substrate; and a first wire connecting the first pad and the third pad; and a second wire connecting the second pad and the wiring substrate.