Stacked Semiconductor Chip Back Surface Terminals for Independent Testing
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Solution Overview
Problem
In semiconductor devices using stacked semiconductor chips, it is challenging to independently test and supply power to smaller chips due to their configuration, which restricts direct access to external terminals and hinders individual testing and power supply.
Innovation Solution
The implementation of external terminals on both chips, allowing them to face the same side after assembly, enables independent testing and power supply to each chip, facilitating simultaneous testing and improving operational margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If chips are connected by micro-bumps with element formed surfaces facing each other to reduce parasitic LCR, then data transfer rate is improved, but external terminals of smaller chips become covered and cannot be directly accessed for testing and power supply
Solution Approach 1:
The patent applies dimensionality change by forming external terminals not only on the front surface (element formed surface) but also on the back surface of the semiconductor chip. This allows smaller chips to have accessible external terminals on their back surfaces after stacking, enabling direct testing and power supply without being covered by upper chips, while maintaining the CoC structure with element formed surfaces facing each other for high-speed data transfer.
2Productivity
If smaller chips are stacked under larger chips in CoC configuration, then device integration is improved, but independent testing of smaller chips becomes impossible without going through larger chips
Solution Approach 1:
The patent applies segmentation by separating the functionality of external terminals into different locations: some terminals remain on the front surface for signal transmission, while additional terminals are placed on the back surface for independent testing and power supply. This segmentation allows the smaller chip to be independently accessed and tested without requiring connection through the larger chip, simplifying the testing process while maintaining integrated device structure.
3Device complexity
If power is supplied through the larger chip to the smaller chip, then device structure is simplified, but operation margin of the smaller chip is reduced
Solution Approach 1:
The patent applies self-service by enabling the smaller chip to supply its own power independently through back surface terminals, rather than relying on power transmission through the larger chip. This allows the smaller chip to have dedicated power supply paths and voltage regulation, improving its operation margin and reliability while maintaining a relatively simple overall device structure.
Data Source
AI summary
In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.