Stacked Semiconductor Package Bonding With Non-Uniform Protection Layers
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving increased durability and improved structural stability, particularly in stacked chip configurations where voids at bonding interfaces can lead to reduced reliability.
Innovation Solution
The semiconductor package design includes a stacked configuration of semiconductor chips with non-uniform thickness protection layers and conductive pads, where the upper and lower protection layers have flat interfaces to minimize voids and enhance bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages use uniform thickness protection layers, then manufacturing is simpler, but voids form at bonding interfaces reducing reliability
Solution Approach 1:
The patent applies local quality by making the protection layer thickness non-uniform, specifically thicker at the bonding interface region and thinner at other regions. This localized variation in thickness ensures complete coverage at the bonding interface to prevent voids while maintaining manufacturing feasibility and reducing overall material usage.
2Stability of the object's composition
If semiconductor chips are stacked with standard bonding interfaces, then assembly is straightforward, but voids form at interfaces reducing structural stability
Solution Approach 1:
The protection layer is designed with locally varied thickness where the bonding interface region has increased thickness compared to other regions. This ensures complete coverage and eliminates voids at the critical bonding interface, thereby improving structural stability while maintaining a relatively simple overall structure that does not require complex assembly processes.
3Reliability
If protection layers are made uniformly thin, then material usage is reduced, but voids form at bonding interfaces reducing durability
Solution Approach 1:
The protection layer thickness is optimized locally by being thicker at the bonding interface where durability is critical and thinner at non-critical regions. This localized approach ensures adequate coverage and eliminates voids at the bonding interface to enhance durability while minimizing overall material consumption compared to a uniformly thick protection layer.
Data Source
AI summary
Provided is a semiconductor package including stacked semiconductor chips. Respective ones of the semiconductor chips include a substrate having front and rear surfaces, an interlayer dielectric layer on the front surface of the substrate, a lower protection layer on a bottom surface of the interlayer dielectric layer, lower conductive pads in the lower protection layer, an upper protection layer on the rear surface of the substrate, and upper conductive pads in the upper protection layer. The upper conductive pads of a first one of the semiconductor chips are respectively in contact with the lower conductive pads of an adjacent one of the semiconductor chips. Each of the upper protection layer and the lower protection layer has a non-uniform thickness. Ones of the lower conductive pads have respective thicknesses that are different from each other.