Stacked Semiconductor Package Structure for Reliable Chip Bonding
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization, weight reduction, high performance, high capacity, and high reliability, particularly in stacking semiconductor chips effectively.
Innovation Solution
A semiconductor package design that includes a base with multiple semiconductor chips stacked vertically, connected by patterns and filled with adhesive material layers to secure the chips and cover the connection patterns, enhancing structural integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If semiconductor chips are stacked in multiple stages to achieve miniaturization and weight reduction, then the package size and weight are reduced, but the reliability and structural integrity may be compromised
Solution Approach 1:
The adhesive material layer is applied in advance to the connection patterns before stacking the semiconductor chips. This preliminary action ensures that the adhesive is already in position to provide structural support and electrical connection, preventing potential reliability issues that could arise from improper adhesive placement or insufficient adhesion during the stacking process
Solution Approach 2:
The adhesive material layer acts as an intermediary substance between the connection patterns and the semiconductor chips. It mediates the bonding process, ensuring reliable mechanical attachment and electrical connectivity while accommodating any minor misalignments or surface irregularities, thus maintaining package reliability in the stacked configuration
2Reliability
If connection patterns are used to electrically connect stacked semiconductor chips, then electrical connectivity is achieved, but the exposed connection patterns may reduce structural integrity
Solution Approach 1:
The adhesive material layer merges the functions of structural bonding and electrical connection support. It combines the mechanical attachment function with the function of protecting and stabilizing the connection patterns, thereby simultaneously achieving structural integrity and electrical connectivity without requiring separate protective structures
Solution Approach 2:
The adhesive material layer forms a flexible thin film that covers and protects the connection patterns. This thin film provides mechanical protection and structural support to the vulnerable connection patterns while maintaining the electrical connectivity function, effectively shielding the exposed patterns from mechanical stress and environmental damage
3Strength
If adhesive material layers are used to fill spaces between stacked chips, then structural integrity is improved, but the manufacturing complexity increases
Solution Approach 1:
The adhesive material layer performs multiple functions simultaneously: it provides structural bonding between chips, fills voids to improve mechanical integrity, protects connection patterns, and enables thermal management. This multi-functionality reduces the need for additional separate components or processes, thereby limiting the increase in manufacturing complexity while achieving comprehensive structural improvement
Data Source
AI summary
A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.