Stacked Semiconductor Chip Bonding with Sacrificial Layer Planarization
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in achieving high-density stacked structures with improved electrical performance and driving stability, particularly in vertically stacked semiconductor devices where uneven surfaces can lead to localized gaps and reduced bonding efficiency.
Innovation Solution
The solution involves a semiconductor device design where each chip includes a sacrificial layer with polishing selectivity, allowing for precise stacking and bonding through a polishing process that planarizes the surface, ensuring consistent contact and improved electrical connectivity between chips, and a method of manufacturing that alternates stacking and polishing to maintain uniformity across multiple chip layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging techniques are used to vertically stack semiconductor chips, then high-density stacked structures can be realized, but uneven surfaces lead to localized gaps and reduced bonding efficiency
Solution Approach 1:
A planarization layer is formed on the bonding surface of each semiconductor chip before stacking. This preliminary action ensures that the bonding surfaces are flat and uniform, preventing localized gaps during the bonding process and improving bonding efficiency without requiring post-fabrication surface adjustment.
Solution Approach 2:
The planarization layer acts as an intermediary between the chip structure and the bonding interface. It provides a flat bonding surface while being compatible with the underlying chip structure, enabling reliable direct bonding without compromising the original chip design or requiring additional surface preparation steps.
2Quantity of substance
If multiple chip layers are stacked to increase capacity, then high-capacity devices are achieved, but processing time increases
Solution Approach 1:
The planarization layer is formed on each chip before stacking, allowing multiple chips to be prepared independently and simultaneously. This preliminary preparation enables parallel processing of multiple chips, reducing the overall processing time compared to sequential assembly methods while still achieving high-capacity multi-layer stacking.
3Reliability
If direct bonding is used to connect chips, then electrical performance is improved, but surface unevenness reduces bonding consistency
Solution Approach 1:
The planarization layer is formed on the bonding surface before the direct bonding process. This preliminary planarization ensures that the bonding surfaces are flat and uniform, enabling consistent and reliable direct bonding between chips while maintaining the electrical performance benefits of direct bonding technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical performance and driving stability by ensuring consistent bonding across stacked chips, reducing processing time, and improving productivity through efficient surface planarization and selective polishing.
Implementation Method 1
applying a polishing process to the at least one preliminary second chip to remove at least a portion of the second sacrificial layer
Data Source
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AI summary
A semiconductor device includes a first chip and a second chip stacked on the first chip. The first chip includes a first substrate, a first upper pad on an upper surface of the first substrate, a first upper insulating layer surrounding a lower portion of the first upper pad and a sacrificial layer surrounding an upper portion of the first upper pad. The second chip includes a second substrate, a second upper pad on an upper surface of the second substrate and a second upper insulating layer surrounding the second upper pad, wherein a thickness of the second upper pad is less than a thickness of the first upper pad.