Stacked Semiconductor Chip Bonding to Prevent Voids and Burrs
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving reliable electrical connections and structural integrity when stacking semiconductor chips, leading to issues with bandwidth and performance due to voids and burrs formed during the stacking process.
Innovation Solution
The semiconductor package design incorporates a hybrid bonding method using insulating layers with cover insulating portions that extend into the semiconductor substrates, reducing voids and burrs, and ensuring reliable electrical connections by forming covalent bonds between insulating layers and conductive material layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are stacked to increase integration and bandwidth, then device capacity and performance are improved, but voids and burrs form during the stacking process that degrade electrical connection reliability
Solution Approach 1:
The patent applies preliminary action by forming protrusions on the insulating layers before the stacking process. These protrusions are created in advance to fill potential voids and prevent burr formation during subsequent chip stacking, thereby maintaining electrical connection reliability while enabling increased device capacity through stacking.
Solution Approach 2:
The patent implements preliminary anti-action by creating protrusions that counteract the formation of voids and burrs before they can degrade electrical connections. The protrusions are positioned to preemptively fill spaces where voids would form and to prevent burr formation at bonding interfaces, thus protecting electrical connection reliability in advance.
2Productivity
If conventional stacking methods are used to increase integration, then device capacity is improved, but burrs form that compromise structural integrity
Solution Approach 1:
The patent applies preliminary action by forming protrusions on the insulating layers before stacking to prevent burr formation. These protrusions are created in advance to fill spaces and provide a clean bonding surface, thereby maintaining structural integrity while enabling increased integration through chip stacking.
3Productivity
If chip stacking is performed to achieve high bandwidth, then performance is improved, but voids form that reduce electrical connection reliability
Solution Approach 1:
The patent applies preliminary action by forming protrusions on the insulating layers before the stacking process. These protrusions are created in advance to fill potential voids at bonding interfaces, thereby maintaining electrical connection reliability while enabling high bandwidth performance through increased integration via stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the structural reliability and electrical connection reliability between stacked semiconductor chips, improving the overall performance and bandwidth of the semiconductor package.
Implementation Method 1
forming covalent bonds between insulating layers and conductive material layers
Data Source
AI summary
A semiconductor chip including a semiconductor substrate having an active surface and a non-active surface opposite to each other, a plurality of through electrodes passing through the semiconductor substrate, a plurality of wiring structures on the active surface and electrically connected to the plurality of through electrodes, an inter-wire insulating layer surrounding the plurality of wiring structures, a plurality of front chip connection pads electrically connected to the plurality of wiring structures, a front insulating layer surrounding the plurality of front chip connection pads, on the inter-wire insulating layer, a plurality of rear chip connection pads disposed on the non-active surface and electrically connected to the plurality of through electrodes, and a rear insulating layer surrounding the plurality of rear chip connection pads, on the non-active surface, wherein the front insulating layer includes a cover insulating portion covering a side surface of the inter-wire insulating layer may be provided.