Stacked Chip Bump Structure for Shorter Thermal Paths
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Solution Overview
Problem
Current semiconductor packages face challenges in miniaturization and thermal management, particularly in reducing the distance between stacked semiconductor chips while maintaining effective heat dissipation.
Innovation Solution
The semiconductor package incorporates a bump structure with a solder pattern and pillar pattern, where the solder pattern is disposed in a hole of the redistribution pattern on the first semiconductor chip, allowing for reduced distance between chips and improved thermal conductivity through a reduced underfill layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the distance between stacked semiconductor chips is reduced to miniaturize the package, then the package size is reduced, but the heat dissipation capability deteriorates
Solution Approach 1:
A bump structure is introduced as an intermediary component between the first and second semiconductor chips. This bump structure includes a conductive material that provides a thermal conduction path, enabling efficient heat transfer from the second chip through the bump structure to the first chip, thus maintaining heat dissipation capability while reducing the distance between chips
Solution Approach 2:
The bump structure is formed using composite materials with different thermal conductivities at different locations. The material composition is optimized to provide both mechanical bonding and thermal conduction functions, allowing the package to achieve miniaturization while maintaining effective heat dissipation through the stacked chip structure
2Length of moving object
If the underfill layer thickness is reduced to decrease distance between chips, then the distance between chips is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The bump structure serves as an intermediary that absorbs and compensates for dimensional variations and misalignments between the stacked chips. By providing a compliant interface with controlled thermal and mechanical properties, the bump structure reduces the sensitivity to manufacturing precision requirements while enabling reduced distance between chips
Solution Approach 2:
The physical and chemical parameters of the bump structure are optimized to balance mechanical strength, thermal conduction, and compliance. By adjusting parameters such as material composition, height, and cross-sectional area, the bump structure accommodates manufacturing tolerances while maintaining the reduced chip spacing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration miniaturizes the semiconductor package, reduces the distance between chips, and enhances thermal properties by facilitating efficient heat dissipation from the first semiconductor chip.
Implementation Method 1
a bump structure disposed between the first semiconductor chip and the second semiconductor chip... a solder pattern provided in the hole so as to be in contact with an inner sidewall of the redistribution pattern
Data Source
AI summary
A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.