Stacked-Chip Capacitive Interconnect for Low-Impedance HF Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits with stacked chips face significant impedance issues at high frequencies due to inductive components in micropillar connections, causing signal reflections and losses, which are not effectively addressed by conventional DC connections.
Innovation Solution
Implementing a coupling capacitor in the junction zone between chips, utilizing conductive micro-poles and micro-pillars to create a high-frequency electrical link with low impedance, allowing for compact and efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If micropillars are used to connect stacked chips, then mechanical strength and DC electrical connection are improved, but impedance increases at high frequencies due to inductive components
Solution Approach 1:
The patent introduces a coupling capacitor as an intermediary component in the inter-chip connection path. This capacitor blocks the inductive effects of the micropillar while allowing high-frequency AC signals to pass with low impedance, effectively mediating between the mechanical connection requirement and the electrical performance requirement at high frequencies.
Solution Approach 2:
The patent segments the inter-chip connection function into two separate components: micropillars for mechanical support and DC connection, and a coupling capacitor for high-frequency AC signal transmission. This segmentation allows each component to optimize its specific function without compromising the other.
2Object-affected harmful factors
If a coupling capacitor is used to reduce impedance at high frequencies, then signal transmission is improved, but the device size increases due to the bulky capacitor structure
Solution Approach 1:
The patent transitions from planar capacitor layouts to a three-dimensional stacked configuration. By placing the capacitor vertically between two chips in the Z-dimension, the design充分利用s the third dimension to achieve adequate capacitance value while maintaining a compact footprint in the XY-plane, thus reducing the overall device area.
Solution Approach 2:
The capacitor structure is nested within the inter-chip junction zone, utilizing the vertical space between stacked chips. The capacitor plates are positioned in the interstitial area, effectively nesting the capacitive element within the existing three-dimensional chip stack architecture rather than adding lateral expansion.
3Quantity of substance
If micropoles are used to form capacitor plates, then capacitance per unit area is increased, but manufacturing precision requirements are heightened
Solution Approach 1:
The patent changes the geometric parameters of the capacitor structure by using tall, narrow micropoles rather than short, wide plates. This parameter change increases the surface area for capacitance while reducing the lateral footprint, and the vertical orientation makes the capacitance less sensitive to lateral alignment errors, thereby relaxing manufacturing precision requirements.
Solution Approach 2:
The patent applies local quality by creating high-capacitance regions at specific locations where micropoles are strategically positioned. The micropoles concentrate the capacitive effect in localized vertical columns, achieving high capacitance per unit area in critical signal paths while allowing less precise positioning compared to large planar electrodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The coupling capacitor reduces impedance and signal losses, enabling high-frequency signal transmission with low return losses and efficient use of inter-chip space, while maintaining manufacturing feasibility and alignment tolerances.
Implementation Method 1
a coupling capacitor which is located in a junction area between chips, between the first chip and the second chip, and which allows a high-frequency electrical link
Data Source
Figure 1~3
Figure 4~5
Figure 6~7
AI summary
An integrated circuit (1) comprising a first chip (10) and a second chip (20) joined to one another, the first chip being electrically connected to the second chip by a coupling capacitor (C) which is located in an inter-chip joining region (30) between the first chip and the second chip, the coupling capacitor comprising a first conductive plate (100) in electrical contact with the first chip, and a second conductive plate (200) in electrical contact with the second chip, at least part of the first plate being formed by one or more electrically conductive microposts (110) which each extend from the first chip toward the second chip.