Semiconductor Stacked Structure With Corner Passive Devices for Noise Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In electronic devices with semiconductor packages, power delivery noise occurs during high-speed operation, which affects the performance and capacity of these devices.

Innovation Solution

A semiconductor stacked structure is designed with a first semiconductor chip and multiple second semiconductor chips stacked in the central region, connected via through-electrodes, and incorporating at least one passive device in the corner region of the outer region to reduce noise and enhance signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor chips are stacked in the central region to increase capacity and performance, then the functionality and capacity of the semiconductor package are improved, but power delivery noise occurs during high-speed operation

Engineering Contradiction:
Improvenumber of semiconductor chipsVSAvoidpower delivery noise
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The semiconductor package is divided into distinct functional regions: a central region containing stacked semiconductor chips for high-speed signal processing, and corner regions containing passive devices for power delivery and noise filtering. This spatial segmentation allows each region to perform its specialized function without interfering with others, resolving the noise problem while maintaining high chip density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the semiconductor package are assigned different functional qualities: the central region is optimized for active signal processing with stacked chips, while the corner regions are optimized for power delivery and noise suppression with passive devices. This local differentiation allows the system to achieve both high-speed performance and low noise simultaneously.

Inventive Principle:
Principle #3Local quality

2Speed

If semiconductor chips are stacked in the central region to improve performance, then signal transmission speed is enhanced, but noise interference affects signal quality

Engineering Contradiction:
Improvesignal transmission speedVSAvoidnoise interference
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

Passive devices such as capacitors and inductors are introduced as intermediary elements in the corner regions to filter and suppress noise generated by high-speed signal transmission in the central region. These intermediary components act as noise barriers that protect the high-speed signals from interference while allowing the fast transmission to continue.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-generated harmful factors

If passive devices are placed in the corner region to reduce noise, then power delivery noise is suppressed, but the central region remains optimized for high-speed signals

Engineering Contradiction:
Improvepower delivery noiseVSAvoidspatial arrangement complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The semiconductor package employs an asymmetric layout where passive devices are specifically positioned in the corner regions rather than being uniformly distributed. This asymmetric arrangement strategically places noise-filtering components where they are most effective without disrupting the symmetric stacking of semiconductor chips in the central region, thereby managing complexity while achieving noise suppression.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20250029895A1Semiconductor stacked structure and semiconductor package including the same
Publication Date: 2025.01.23 SAMSUNG ELECTRONICS CO LTD
  • US20250029895A1 patent drawing
  • US20250029895A1 patent drawing
  • US20250029895A1 patent drawing

AI summary

A semiconductor stacked structure includes a first semiconductor chip including, a central region, an outer region at least partially surrounding the central region, the outer region including a corner region, and a first through-electrode in the central region, a plurality of second semiconductor chips sequentially stacked in the central region and connected to the first semiconductor chip, each of the plurality of second semiconductor chips including a second through-electrode, and at least one passive device in the corner region of the outer region.