Stacked Chip Packaging with Chip Couplers for Wafer-Level 3D Integration
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Solution Overview
Problem
Current chip-stacking technologies are complicated and costly due to the need for vertical connections between stacked chips using methods like Through Silicon Via (TSV), Through Glass Via (TGV), or Wire-bond, which are not supported by conventional Wafer Level Packaging (WLP) processes.
Innovation Solution
A method for forming a package of stacked chips using chip couplers with through vias and a redistribution layer, allowing wafer-level chip stacking without TSV, TGV, or Wire-bond, and enabling a one-stop WLP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip stacking technology is used with TSV, TGV, or Wire-bond for vertical connections, then vertical connection between stacked chips is achieved, but the packaging process becomes complicated and costly
Solution Approach 1:
The patent extracts the vertical connection function from complex TSV/TGV/Wire-bond processes and relocates it to the carrier substrate level. By forming through-vias and redistribution layers on the carrier substrate before chip stacking, the invention eliminates the need for post-stack vertical connection processes, thereby simplifying the overall packaging process while maintaining reliable vertical connections between stacked chips
Solution Approach 2:
The patent performs preliminary actions by pre-forming through-vias, pad structures, and redistribution layers on the carrier substrate before stacking chips. This preliminary preparation of connection infrastructure enables subsequent chip layers to be directly connected without requiring complex post-assembly vertical connection processes, thus reducing packaging complexity while ensuring connection reliability
2Reliability
If conventional chip stacking technology with TSV, TGV, or Wire-bond is used, then vertical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the costly TSV/TGV/Wire-bond vertical connection processes and replaces them with a simplified carrier substrate-based connection approach. By forming all necessary through-vias and redistribution layers on the carrier substrate before stacking, the invention eliminates expensive post-stack processing steps, thereby reducing manufacturing cost while maintaining vertical connection functionality
Solution Approach 2:
The patent merges multiple separate processes (via formation, pad creation, redistribution layer deposition) into a single integrated sequence performed on the carrier substrate before stacking. This consolidation of processes into one unified workflow eliminates redundant steps and reduces overall manufacturing complexity and cost, while ensuring reliable vertical connections between stacked chips
3Productivity
If Wafer Level Packaging (WLP) is used, then integration of wafer fab, packaging, test, and burn-in is streamlined, but chip-stacking is not allowed
Solution Approach 1:
The patent extends conventional planar WLP into the vertical dimension by forming three-dimensional structures (through-vias, stacked pad structures, redistribution layers) on the carrier substrate. This vertical expansion of WLP methodology enables chip stacking capability while preserving the integrated wafer-level manufacturing process, thereby achieving both process integration and stacking versatility
Solution Approach 2:
The patent creates a universal carrier substrate platform that can accommodate both conventional WLP processes and chip stacking operations. By designing the carrier substrate with integrated through-vias, pad structures, and redistribution layers that serve multiple functions, the invention enables a single WLP process to handle both planar packaging and vertical stacking, thus achieving adaptability without sacrificing productivity
Data Source
AI summary
A method of forming a package is provided. The method comprises assembling on a carrier a stack of chip layers including a plurality of first chip layers and a second chip layer; encapsulating the stack of chip layers in a molding compound; removing the carrier to form a package main body; forming a redistribution layer on an exposed side of a first chip layer; and dividing the package main body to form a plurality of packages. Each first chip layer includes first chips and chip couplers. A chip package includes at least one chip stack and at least one chip coupler stack on a singulated redistribution layer. Each chip stack includes at least one chip from each chip layer, and each chip coupler stack includes at least one chip coupler and/or at least one chip coupler segment from each of the first chip layers.