Stacked Chip Crack Detection Circuit for Package Interface Monitoring
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Solution Overview
Problem
Current semiconductor devices lack effective methods for detecting cracks in stacked semiconductor chips during the cutting and packaging process, which can lead to defective products and are not suitable for advanced semiconductor packages with multiple chips.
Innovation Solution
A semiconductor device with a crack detection circuit that includes first and second crack detection lines passing through interfaces between stacked semiconductor chips, and a crack detector configured to transmit test signals and receive reception signals to detect cracks, allowing for precise identification of crack locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked in advanced packages, then device functionality and integration are improved, but the complexity of detecting cracks during cutting and packaging increases
Solution Approach 1:
The crack detection circuit is segmented into multiple independent detection lines (first crack detection line, second crack detection line, third crack detection line) that can be distributed across different chip stacks. Each detection line independently monitors cracks in specific regions, allowing the system to scale to multiple chips without increasing overall system complexity.
Solution Approach 2:
The crack detection lines are configured to extend in multiple spatial dimensions - horizontally across chip interfaces and vertically through stacked layers. This multi-dimensional arrangement enables comprehensive crack detection in three-dimensional stacked packages, transforming the detection problem from a single-plane issue to a volumetric monitoring system.
2Measurement precision
If crack detection lines pass through interfaces between stacked chips, then detection precision is improved, but device complexity increases
Solution Approach 1:
The crack detection lines serve multiple functions: they detect cracks at chip interfaces, monitor internal chip structures, and provide spatial localization information. By making the detection lines multi-functional, the patent reduces the need for separate detection mechanisms for each function, thereby managing complexity while maintaining high precision.
Solution Approach 2:
The detection lines are nested within the existing chip stack structure, with lines positioned to pass through interfaces and contact surfaces of stacked chips. This nesting approach integrates the detection circuitry into the package architecture without requiring separate external monitoring systems, reducing overall device complexity.
3Measurement precision
If a crack detector transmits test signals through multiple crack detection lines, then detection accuracy is improved, but energy consumption increases
Solution Approach 1:
The crack detector transmits test signals periodically rather than continuously through the crack detection lines. This periodic action maintains detection accuracy by regularly monitoring for cracks while significantly reducing energy consumption compared to continuous signal transmission.
Data Source
AI summary
A semiconductor device includes a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip, wherein a type of the second semiconductor chip is different from a type of the first semiconductor chip; and a crack detection circuit including: a first crack detection line repeatedly passing through an interface between the first semiconductor chip and the second semiconductor chip; a second crack detection line including a bonding pad or a through-via structure contacting a surface of the second semiconductor chip opposite to the interface; and a crack detector in the second semiconductor chip, the crack detector being configured to output a first test signal to the first crack detection line, receive a first reception signal from the first crack detection line, output a second test signal to the second crack detection line, and receive a second reception signal from the second crack detection line.