Stacked Semiconductor Chip Crack Detection via TSV Test Terminals
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Solution Overview
Problem
Existing semiconductor chip crack detection methods fail to identify cracks in individual chips within a stack of semiconductor devices, as the detection structures are not designed to differentiate between chips when they are stacked.
Innovation Solution
A semiconductor device with vertically stacked chips connected via through silicon vias (TSVs), featuring signal terminals, common test terminals, and spiral test terminals, allowing for the measurement of resistance changes along the periphery to detect cracks in each chip within the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common test terminal structure is used for stacked semiconductor chips, then the device complexity is reduced, but the ability to detect cracks in individual chips is lost
Solution Approach 1:
The patent divides the common test terminal structure into chip-specific segments. Each semiconductor chip is assigned unique combinations of common test terminals and spiral test terminals, allowing individual chip identification and crack detection within the stacked configuration. This segmentation enables precise measurement of resistance changes in each chip without requiring separate external test terminals for every chip.
Solution Approach 2:
The patent implements local quality by providing each chip with its own spiral test terminals in addition to shared common test terminals. The spiral test terminals are locally positioned on each chip to detect cracks specific to that chip, while the common test terminals are shared across multiple chips. This combination allows the system to maintain simplicity while achieving localized crack detection capability.
2Measurement precision
If spiral test terminals are added to each chip, then crack detection precision is improved, but the device complexity increases
Solution Approach 1:
The patent merges the common test terminals (shared across multiple chips) with chip-specific spiral test terminals to create a unified test structure. This combination allows the system to achieve high measurement precision through the spiral terminals while maintaining relatively low device complexity by sharing the common terminals across multiple chips, rather than providing completely separate test structures for each chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the identification of cracks in each semiconductor chip within a stacked configuration by measuring resistance changes through the conductive lines and test terminals, ensuring accurate detection even in multi-layered chip stacks.
Implementation Method 1
detects existence of the crack by measuring resistance of an electric conductor provided in a periphery of the semiconductor chip
Data Source
AI summary
A semiconductor device includes a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias, a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via, and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.