Stacked Semiconductor Chip Bonding Structure for Crack Resistance
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Solution Overview
Problem
In semiconductor device packaging, the arrangement of memory chips over a controller chip with a thick Die Attach Film (DAF) can lead to stress concentration and crack formation due to thermal expansion differences, potentially causing electrical failures like disconnection defects.
Innovation Solution
A semiconductor device configuration that includes a substrate, a controller chip, memory chips, a bonding layer, and a member with higher strength than the sealing resin, where the member is positioned on the outer periphery of the bonding layer to prevent crack formation by distributing stress and reducing the influence of thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a thick DAF (Die Attach Film) is used to arrange the memory chip over the controller chip, then the memory chip can be positioned to cover the controller chip, but stress concentration and crack formation occur due to thermal expansion differences
Solution Approach 1:
The patent applies local quality by providing a reinforcement member (such as a rigid or semi-rigid substrate) specifically at the region where the memory chip is mounted over the controller chip. This localized reinforcement strengthens the area prone to stress concentration and crack formation due to thermal expansion differences, while leaving other areas of the package structure unchanged. The reinforcement member has different mechanical properties than the surrounding sealing resin, creating a localized zone of enhanced strength and crack resistance.
2Adaptability or versatility
If a thick DAF is used for chip arrangement, then positioning flexibility is improved, but the bonding layer becomes more susceptible to thermal expansion stress
Solution Approach 1:
The patent implements beforehand cushioning by placing a reinforcement member in advance within the bonding layer or adjacent to it, specifically at positions where thermal expansion stress is expected to concentrate. This reinforcement member acts as a preventive measure that cushions and distributes the thermal expansion stress before it can cause damage to the bonding layer or create cracks in the chip arrangement structure.
3Ease of operation
If the bonding layer is made thicker to accommodate chip arrangement, then chip positioning is easier, but stress concentration increases leading to potential disconnection defects
Solution Approach 1:
The patent introduces an intermediary reinforcement member (such as a rigid substrate, ceramic plate, or metal layer) within the bonding layer structure that acts as a mediator between the memory chip and the controller chip. This intermediary distributes the thermal expansion stress across a larger area, preventing stress concentration at any single point. The reinforcement member serves as a stress-distributing interface that maintains the integrity of the bonding layer while accommodating the thick DAF required for chip positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively restrains crack formation and reduces the risk of electrical failures by providing a strong member that absorbs stress, ensuring the reliability and integrity of the semiconductor package.
Implementation Method 1
stress concentration and crack formation due to thermal expansion differences
Implementation Method 2
distributing stress and reducing the influence of thermal expansion
Data Source
AI summary
A semiconductor device according to the present embodiment includes a substrate, a first semiconductor chip, a second semiconductor chip, a bonding layer, and a member. The substrate has a first surface. The first semiconductor chip is provided on the first surface. The second semiconductor chip is provided above the first semiconductor chip, has a second surface facing the first surface and the first semiconductor chip, and coats the first semiconductor chip as viewed from a direction substantially perpendicular to the first surface. The bonding layer is provided between the second surface and both the first surface and the first semiconductor chip. The member is provided on at least part of an outer periphery of the bonding layer as viewed from the direction substantially perpendicular to the first surface.