Stacked Semiconductor Package Layout for Thermal Expansion Matching
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Solution Overview
Problem
The electronics industry faces challenges in creating small, high-performance semiconductor packages that maintain excellent electrical characteristics and structural stability, particularly for high-frequency signal processing, as existing techniques struggle to integrate multiple semiconductor chips efficiently while minimizing size and ensuring thermal expansion compatibility.
Innovation Solution
A semiconductor package design featuring stacked semiconductor chips with distinct molding layers of different materials, where the second molding layer has a higher hardness and specific thermal expansion properties, and through-electrodes form a single body with chip pads for direct electrical connection without intermediate components, enhancing structural stability and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are integrated in a single package, then the electronic component size is reduced, but the thermal expansion compatibility and structural stability deteriorate
Solution Approach 1:
The patent divides the molding structure into multiple distinct molding layers (first molding layer and second molding layer) with different materials, each having different coefficients of thermal expansion. This segmentation allows each layer to accommodate thermal expansion differently, resolving the thermal expansion compatibility issue while maintaining the compact multi-chip package structure.
Solution Approach 2:
The patent uses composite molding materials with different thermal expansion properties in different layers. The first molding layer and second molding layer are formed of different materials specifically selected to match the thermal expansion characteristics of the underlying chips, creating a composite structure that maintains structural stability under thermal stress.
2Volume of moving object
If multiple semiconductor chips are integrated in a single package, then the electronic component size is reduced, but the electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from planar chip arrangement to vertical stacking in the third dimension, allowing multiple chips to be integrated in a compact volume while maintaining short electrical connection paths through through-electrodes, thus preserving electrical characteristics.
Solution Approach 2:
The patent removes intermediate connection components (such as separate bonding wires or intermediate substrates) by directly connecting chip pads to through-electrodes, simplifying the electrical connection path and improving signal integrity in the high-frequency range.
3Device complexity
If through-electrodes are used for direct electrical connection, then the device complexity is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent merges the chip pad and through-electrode into a single integrated structure, eliminating the need for separate bonding processes and intermediate components. This reduces device complexity while the formation process itself ensures proper alignment, balancing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved electrical performance, miniaturization, and structural stability by eliminating the need for intermediate electrical connections and ensuring thermal expansion compatibility, reducing warpage and enhancing the overall reliability of the semiconductor package.
Implementation Method 1
a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1
Data Source
AI summary
A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.