Stacked Semiconductor Package Layout for Non-Destructive Alignment Inspection
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Solution Overview
Problem
Current semiconductor packages face challenges in performing non-destructive testing and ensuring precise alignment of stacked chips, which is crucial for high-density and high-performance electronic devices.
Innovation Solution
The semiconductor package design includes vertically stacked substrates with chip pads and dummy pads, where the distance between dummy pads is carefully controlled to allow for non-destructive testing and precise alignment of chips, utilizing penetration electrodes and insulating layers for electrical connections and alignment accuracy measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor package testing methods are used, then testing can be performed, but the testing process is destructive and cannot ensure precise alignment of stacked chips
Solution Approach 1:
The patent uses dummy pads as test targets that replicate the electrical and geometric characteristics of actual chip pads without requiring functional operation of the semiconductor devices. These dummy pads are formed on the substrate surface and serve as alignment reference points for optical or electron microscopy systems, enabling non-destructive measurement of chip stacking alignment accuracy.
Solution Approach 2:
The patent introduces dummy pads as intermediary elements between the chip stacking process and the alignment measurement process. These dummy pads act as mediators that allow external measurement systems to access and evaluate alignment accuracy without requiring contact with or operation of the actual functional pads, thus enabling non-destructive testing.
2Quantity of substance
If chip size is reduced for high-density devices, then device density increases, but alignment precision becomes more difficult to achieve and measure
Solution Approach 1:
The patent separates the measurement function from the functional pads by creating dedicated dummy pads that are spatially distinct from the operational chip pads. This segmentation allows the measurement system to focus exclusively on alignment assessment without interference from functional device operations, enabling precise measurement even as functional pads become smaller for high-density applications.
Solution Approach 2:
The patent applies local quality by creating specific regions (dummy pad areas) with enhanced measurement characteristics on the substrate surface. These localized regions provide high-contrast, well-defined targets for alignment measurement, while the rest of the substrate maintains its functional device structures with reduced pad sizes for high density.
3Productivity
If multiple chips are stacked vertically for high integration, then device capacity increases, but alignment accuracy among stacked chips becomes more critical and difficult to control
Solution Approach 1:
The patent implements preliminary action by pre-forming dummy pads on the substrate surface before chip stacking. These dummy pads are positioned at predetermined locations that correspond to the expected chip pad locations, establishing reference points in advance that guide the alignment process during chip stacking and enable post-stack alignment verification.
Solution Approach 2:
The patent establishes a feedback mechanism where the position and integrity of dummy pads serve as indicators of alignment accuracy in stacked chips. By measuring the alignment between dummy pads across different stacking layers, the system provides feedback on manufacturing precision, allowing for process adjustment and quality control in high-density multi-chip stacking operations.
Data Source
AI summary
A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.