Stacked Semiconductor Chip Pads for NCF Void and Warpage Control

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Solution Overview

Problem

In semiconductor chip stacking, insufficient dispersion of non-conductive film (NCF) between chips can lead to voids and warpage due to pressing phenomena in corner regions, causing structural instability in stacked semiconductor packages.

Innovation Solution

The use of dummy pads with higher heights than bonding pads on the semiconductor chips, strategically placed in corner regions, supports adjacent chips and prevents adhesive spread, ensuring proper alignment and attachment of stacked semiconductor chips with a non-conductive film filling the spaces between them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If non-conductive film is used to fill space between stacked semiconductor chips, then adhesive coverage is improved, but voids occur in corner regions due to insufficient dispersion

Engineering Contradiction:
Improveadhesive coverageVSAvoidvoid formation
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces dummy pads specifically in corner regions with different properties (height, material composition) compared to central bonding pads. These localized structural modifications enable the adhesive to properly disperse and fill corner voids while maintaining adequate coverage in central regions, resolving the contradiction between adhesive quantity and void prevention.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dummy pads are pre-formed on the semiconductor chip before stacking, creating preliminary support structures in corner regions. This preliminary action ensures that when adhesive is applied, it can properly disperse from the beginning, preventing void formation before the bonding process completes.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If corner regions are left without support structures, then device complexity is reduced, but warpage occurs due to pressing phenomena

Engineering Contradiction:
Improvestructure simplicityVSAvoidchip warpage
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

Rather than adding complex support structures throughout the entire chip, the patent applies local quality by introducing dummy pads only in corner regions where pressing phenomena and warpage occur. This minimal, targeted approach maintains overall structural simplicity while effectively preventing warpage.

Inventive Principle:
Principle #3Local quality

3Stability of the object's composition

If dummy pads with higher height are added in corner regions, then warpage prevention is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvewarpage preventionVSAvoidpad height control
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The patent utilizes parameter changes by varying the height of dummy pads relative to bonding pads. The dummy pads are formed with a first height and bonding pads with a second height, where the height difference creates the necessary support effect. This parameter variation is achieved through controlled deposition or formation processes that can precisely manage thickness and height parameters.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240063186A1Semiconductor package including stacked chips and method of manufacturing the semiconductor package
Publication Date: 2024.02.22 SAMSUNG ELECTRONICS CO LTD
  • US20240063186A1 patent drawing
  • US20240063186A1 patent drawing
  • US20240063186A1 patent drawing

AI summary

A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite thereto. The substrate has a central region and corner regions surrounding the central region. A plurality of through electrodes passes through the central region. A bonding pad is electrically connected to the through electrode and has a first height. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and have a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite thereto. The second semiconductor chip is disposed on the first semiconductor chip through conductive bumps disposed on the second lower surface and electrically connected to the bonding pads.