Stacked Through-Electrode Chip Package With Dummy Thermal Vias
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high performance, high capacity, and miniaturization while maintaining reliability, particularly in stacked semiconductor chips with through silicon vias.
Innovation Solution
A semiconductor package design incorporating first and second semiconductor chips connected by through electrodes, with a third semiconductor chip featuring dummy electrode structures for improved heat dissipation, and encapsulation to enhance reliability and reduce signal transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in a perpendicular direction to achieve miniaturization and high capacity, then device density and capacity are improved, but heat dissipation becomes more difficult and reliability deteriorates
Solution Approach 1:
The patent divides the chip stack into multiple segments with different functions: computing chips (first and second chips) and dummy chips (third and fourth chips). The dummy chips are specifically designed to act as heat dissipation structures, segmenting the thermal management function from the computing function. This allows heat generated by the computing chips to be dissipated through the dummy chips, resolving the heat dissipation problem while maintaining high device capacity through vertical stacking.
2Speed
If through silicon vias are used to connect stacked chips, then signal transmission paths are reduced and performance is improved, but manufacturing complexity and reliability challenges increase
Solution Approach 1:
The patent incorporates dummy chips with dummy electrode structures that serve as cushioning elements. These dummy electrodes provide mechanical support and stress distribution around the through silicon vias, cushioning against manufacturing variations and thermal stress. This beforehand cushioning approach prevents via breakage and improves reliability while maintaining the short signal transmission paths enabled by the stacked chip architecture.
3Productivity
If the number of chips in the stack is increased to improve performance, then device performance and capacity are enhanced, but manufacturing yield and reliability deteriorate
Solution Approach 1:
The patent uses dummy chips with dummy electrode structures that have the same physical dimensions and material composition as the through electrodes in functional chips. This homogeneity allows all chips in the stack to be manufactured using the same processes and materials, simplifying manufacturing and improving yield. The dummy chips serve as test structures that validate the manufacturing process without adding functional complexity, thereby enhancing overall manufacturing yield while enabling high-performance multi-chip stacks.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including first pads and a first insulating layer, and a second semiconductor chip including second upper pads, a second insulating layer, second lower pads, and through electrodes connecting the second upper pads and the second lower pads to each other. The package includes a third semiconductor chip including third upper pads, an upper barrier layer, a third insulating layer, third lower pads, a lower barrier layer, and dummy electrode structures connecting the third upper pads and the third lower pads to each other. The package includes an encapsulant below the first semiconductor chip to seal at least a portion of each of the second and third semiconductor chips and cover side surfaces of the third lower pads. The package includes bump structures below the encapsulant and the second and third semiconductor chips.