Stacked Chip Interposer for Independent DVFS Supply Forwarding
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Solution Overview
Problem
Existing DVFS techniques are inefficient in multi-chip assemblies with IC dies from different process nodes and varying skew, as they force all dies to operate at the same DVFS point, leading to sub-optimal power optimization.
Innovation Solution
A microelectronic assembly with a first IC die in a first layer and an interposer in a second layer, connected by interconnects with a pitch of less than 10 micrometers, allows independent DVFS operating points across multiple IC dies through forwarded supply voltages, optimizing FV curves for each chiplet.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If all IC dies are forced to operate at the same DVFS point, then system synchronization is maintained, but power optimization becomes sub-optimal
Solution Approach 1:
The patent segments the multi-chip system into independent voltage control domains by introducing separate voltage regulation modules for each IC die. This allows each die to be controlled independently rather than forcing uniform DVFS across all dies, thereby achieving both synchronization stability and optimal power efficiency for each segment based on its specific process node and skew characteristics.
Solution Approach 2:
The patent applies local quality by allowing each IC die to have customized DVFS parameters tailored to its specific process node and skew characteristics. Instead of a uniform DVFS policy, each die can operate at its optimal voltage-frequency point, with local voltage regulation and monitoring implemented at each die level to maintain system-wide synchronization while optimizing individual power consumption.
2Adaptability or versatility
If IC dies from different process nodes are used, then manufacturing flexibility and performance optimization are improved, but coordinating DVFS operation across dies becomes more complex
Solution Approach 1:
The patent introduces an intermediary voltage regulation and coordination layer that manages DVFS operations across IC dies from different process nodes. This intermediary structure includes central coordination logic that communicates with individual die regulators, allowing flexible mixing of process nodes while managing the complexity of DVFS coordination through a standardized interface and centralized control mechanism.
3Use of energy by moving object
If supply voltage is reduced to lower power consumption, then energy efficiency improves, but execution time increases due to slowed clock frequency
Solution Approach 1:
The patent implements dynamic DVFS control that continuously monitors workload demands and adjusts supply voltage and frequency in real-time. This dynamic approach allows the system to operate at lower voltages and frequencies during low-demand periods to improve energy efficiency, while quickly scaling up voltage and frequency when performance is needed, thereby minimizing execution time loss while maximizing energy efficiency across different operating conditions.
Data Source
AI summary
Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die. The first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die, the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and the first supply voltage is different from the second supply voltage.