Stacked Chip Package Edge Circuit Layout Without TSVs
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Solution Overview
Problem
Conventional chip packages with through silicon vias (TSV) are labor-intensive and increase manufacturing costs due to complex internal circuit design requirements, as the TSV formation process is time-consuming and complicates external electrical connections.
Innovation Solution
A chip package unit with a first and second redistribution layer (RDL) and a first circuit layer located on lateral sides, allowing for simplified manufacturing by cutting wafers and forming conducting through holes to connect the chip with external circuits, reducing manufacturing complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon via (TSV) is used for vertical electrical connection, then electrical connection between front surface and back surface is achieved, but manufacturing process becomes labor and time consuming
Solution Approach 1:
The patent transitions from vertical through-silicon connections (TSV) to lateral edge-based connections. The circuit layer is disposed on the lateral edge of the chip, extending from the front surface to the back surface, enabling electrical connection without penetrating through the chip thickness. This dimensional shift from vertical to lateral connectivity resolves the manufacturing complexity of TSV while maintaining electrical connection functionality.
2Reliability
If through silicon via (TSV) is used for vertical electrical connection, then front surface or back surface can be electrically connected to outside, but internal circuit design becomes more difficult
Solution Approach 1:
The circuit layer is positioned on the lateral edge of the chip rather than requiring vertical TSV paths through the chip substrate. This lateral edge configuration allows internal circuits to be designed without avoiding TSV positions, as the electrical connection path is repositioned to the chip perimeter, significantly reducing circuit design constraints and complexity.
3Reliability
If through silicon via (TSV) is used, then vertical electrical connection is achieved, but manufacturing cost is increased
Solution Approach 1:
By relocating the electrical connection path from vertical TSV through the chip to a lateral circuit layer on the chip edge, the manufacturing process avoids the complex and costly TSV formation steps. The lateral configuration enables simpler fabrication processes while maintaining reliable electrical connection between front and back surfaces.
Data Source
AI summary
A chip package unit, a method of manufacturing the same, and a package structure formed by stacking the same are provided. The chip package unit is formed by cutting of a wafer separately. The chip package unit includes a chip, a first redistribution layer (RDL), a second RDL, and at least one first circuit layer. The first circuit layer is electrically connected with and disposed between a first conductive circuit and a second conductive circuit. The first circuit layer is located at least one first lateral side of the chip, at least one second lateral side of the first RDL, and at least one third lateral side of the second RDL. The chip can be electrically connected with the outside by the first conductive circuit or the second conductive circuit. Thereby manufacturing process is simplified and manufacturing cost is further reduced.