Stacked Semiconductor Chip Bonding Pads for Edge Void Reliability
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Solution Overview
Problem
In semiconductor packages with stacked semiconductor chips, bonding voids can occur between pads adjacent to the edge region of the adhesive surface, leading to potential differences between adjacent pads, which can cause conductive materials to move through these voids, resulting in circuit shorts and reduced reliability.
Innovation Solution
The semiconductor package design includes edge bonding pads in the edge region of the first semiconductor chip, arranged in a specific direction parallel to the chip's edge, where these pads are of the same type (power, ground, or dummy) and receive the same voltage, preventing potential differences and conductive material movement through bonding voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are stacked in a vertical direction with hybrid bonding, then high-performance electronic devices can be achieved, but bonding voids occur between pads adjacent to the edge region
Solution Approach 1:
The patent applies different pad arrangement strategies to different regions of the chip. Specifically, edge region pads are arranged with the same type (all power, all ground, or all dummy) to eliminate potential differences, while central region pads can have alternating types. This localized differentiation resolves the bonding void issue at edges without compromising the overall stacking density and performance.
2Adaptability or versatility
If pads of different types (power and ground) are adjacent to each other in the edge region, then electrical functionality is achieved, but potential difference causes conductive material to move through bonding voids
Solution Approach 1:
The patent creates equipotential regions by arranging pads of the same type (same voltage level) adjacent to each other in the edge region. This eliminates potential differences between adjacent pads, preventing electrostatic forces that would drive conductive material through bonding voids. The equipotential arrangement maintains electrical functionality while eliminating the reliability risk.
3Adaptability or versatility
If edge bonding pads are arranged with alternating types to optimize electrical performance, then circuit functionality is improved, but conductive material movement through bonding voids increases
Solution Approach 1:
The patent differentiates pad arrangement by region: edge region pads are arranged with the same type to prevent conductive material migration, while central region pads can use alternating types for optimized electrical performance. This localized quality differentiation resolves the contradiction by applying the appropriate arrangement strategy to each region's specific requirements.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip and a second semiconductor chip thereon. The first semiconductor chip includes upper bonding pads at an upper portion thereof. The second semiconductor chip includes lower bonding pads at a lower portion thereof. The first semiconductor chip and the second semiconductor chip are connected through direct contact between the upper bonding pads and lower bonding pads. The upper bonding pads include edge bonding pads on an edge region of the first semiconductor chip and arranged in a first direction parallel to an edge of the first semiconductor chip. The edge bonding pads include a first edge pad and a second edge pad disposed adjacent to each other. The each of the first and second edge pads is one of a power pad, a ground pad, and a dummy pad, and the first and second edge pads are of the same type.