Stacked Semiconductor Chip-Embedded Substrate for High Density
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Solution Overview
Problem
Current semiconductor chip-embedded substrates fail to achieve high packaging density and miniaturization while maintaining reliability, as they are limited by positioning accuracy and material expansion differences.
Innovation Solution
The substrate embeds semiconductor chips in a stacked configuration within an insulating layer on a supporting substrate, with electrical connections via wire bonding or through-holes, and uses electro-conductive materials to connect chips, allowing for high-density embedding and reduced warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are mounted on a substrate in conventional methods, then the substrate can be manufactured with standard processes, but the packaging density is low and the substrate size is large
Solution Approach 1:
The patent transitions from planar chip mounting to three-dimensional stacked chip embedding. Multiple semiconductor chips are arranged in stacks vertically within the substrate, utilizing the depth dimension to increase packaging density. This allows multiple chips to occupy the same footprint area by stacking them in the vertical direction, thereby reducing the overall substrate size while accommodating more chips.
Solution Approach 2:
The patent embeds semiconductor chips within cavities or recesses formed in the substrate, effectively nesting the chips inside the substrate structure. This nesting approach allows the chips to be partially or fully contained within the substrate volume, maximizing the use of available space and increasing packaging density without proportionally increasing substrate area.
2Area of stationary object
If chips are embedded in a substrate to increase packaging density, then miniaturization is achieved, but positioning accuracy decreases and warping increases
Solution Approach 1:
The patent divides the substrate into multiple regions with individual cavities or recesses, each designed to hold a specific semiconductor chip or stack. This segmentation provides predetermined positioning locations that guide chip placement, ensuring accurate positioning even in three-dimensional configurations. The segmented structure also helps isolate thermal and mechanical stresses, reducing warping.
Solution Approach 2:
The patent employs asymmetric cavity designs and non-uniform chip stacking arrangements to compensate for differential thermal expansion and contraction. By strategically positioning cavities and stacks with varying depths and configurations, the design balances internal stresses and prevents warping, maintaining manufacturing precision despite the complex embedded structure.
3Quantity of substance
If chips are stacked to increase packaging density, then miniaturization is achieved, but reliability decreases due to material expansion differences
Solution Approach 1:
The patent applies different materials and structural configurations to different regions of the substrate based on local requirements. Cavities near chip stacks may have enhanced thermal management features or stress-compensating structures, while other regions use standard substrate materials. This localized optimization addresses material expansion differences at specific hotspots, maintaining overall reliability while achieving high packaging density.
Solution Approach 2:
The patent utilizes composite material structures combining substrate materials with different thermal and mechanical properties. The substrate may incorporate layers with varying coefficients of thermal expansion to match those of the semiconductor chips, reducing stress from differential expansion. Composite materials are also used in the cavity structures and interconnect layers to accommodate thermal cycling and maintain reliability in stacked chip configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a thin, miniature substrate with enhanced reliability and reduced warping, achieving higher packaging density and improved precision by utilizing pre-stacked chips, which are symmetrically disposed on both sides of the substrate.
Implementation Method 1
electrical connections via wire bonding or through-holes, and uses electro-conductive materials to connect chips
Implementation Method 2
electrical connections via wire bonding
Data Source
AI summary
A semiconductor chip-embedded substrate comprising a supporting substrate and an insulating layer thereon, members for the connection to external circuits, and a plurality of semiconductor chips embedded in the insulating layer, wherein at least some of the plurality of semiconductor chips are embedded as a stack or stacks thereof. A method of manufacturing such a semiconductor chip-embedded substrate is also disclosed.