Stacked Chip Package With Chemically-Etched Surface

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Solution Overview

Problem

As chip sizes and thicknesses decrease, the packaging process becomes increasingly difficult, posing challenges in preventing chip damage and ensuring the structural stability and reliability of chip packages.

Innovation Solution

A chip package is formed by stacking two chips with a chemically-etched surface and a bonding bulk between them, using a method that involves forming a bonding bulk between substrates, creating a through-hole, and partially removing the substrate to form separate chip packages, thereby enhancing structural stability and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If chip size and thickness are decreased, then integration density is improved, but manufacturing difficulty and reliability deteriorate

Engineering Contradiction:
Improvechip sizeVSAvoidchip package reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

A buffer layer is formed between the first chip and second chip to absorb thermal stress and mechanical stress during the packaging process. This buffer layer acts as a cushion that prevents stress concentration on the thin chips, thereby maintaining high reliability even as chip thickness decreases for greater integration density.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent employs a composite structure consisting of multiple layers including the first chip, buffer layer, bonding bulk, and second chip. This composite material approach allows each layer to contribute its specific properties (mechanical strength, stress absorption, bonding capability) to collectively enhance the overall reliability of the packaged device while enabling smaller chip dimensions.

Inventive Principle:
Principle #40Composite materials

2Volume of moving object

If chip size and thickness are decreased, then integration density is improved, but structural stability deteriorates

Engineering Contradiction:
Improvechip sizeVSAvoidstructural stability
Core Design Contradiction:
Volume of moving objectVSStability of the object's composition

Solution Approach 1:

The buffer layer is positioned between the two chips to provide mechanical cushioning and stress distribution. This prevents direct stress transmission between chips, maintaining structural stability even when chips are thinned to achieve higher integration density.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The buffer layer and bonding bulk serve as intermediary elements between the first chip and second chip. These intermediary structures provide mechanical support and stress distribution, ensuring structural stability of the stacked configuration while allowing the use of smaller, thinner chips for improved integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If conventional packaging methods are used, then process simplicity is maintained, but chip damage risk increases

Engineering Contradiction:
Improvepackaging process complexityVSAvoidchip damage prevention
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The buffer layer is formed beforehand between the chips before final bonding, providing stress absorption during subsequent packaging operations. This advance cushioning measure protects chips from damage during handling and processing while adding only one additional fabrication step.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The buffer layer and bonding bulk are prepared in advance before the chips are stacked and bonded together. This preliminary preparation ensures that protective structures are in place before chips undergo potential stress during packaging, reducing damage risk while maintaining relatively simple overall process flow.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the reliability of the chip package, reducing the likelihood of damage during the packaging process and maintaining structural stability, even as chip sizes and thicknesses decrease.

Implementation Method 1

wherein a side surface of the second chip is a chemically-etched surface

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS9305843B2Chip package and method for forming the same
Publication Date: 2016.04.05 XINTEC INC
  • US9305843B2 patent drawing
  • US9305843B2 patent drawing
  • US9305843B2 patent drawing

AI summary

An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.