Stacked Chip Failure Detection for Pixel-Parallel AD Imaging
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Solution Overview
Problem
Pixel-parallel AD imaging devices require comprehensive failure detection due to the large number of latch circuits, which is not adequately addressed by existing technologies, especially in comparison to column AD imaging devices.
Innovation Solution
A stacked chip structure with two semiconductor chips, where one chip includes a pixel circuit with a photoelectric conversion element and the other includes an analog-to-digital conversion circuit with a latch circuit and a failure detection circuit that writes and reads a test pattern to detect failures without actual imaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel-parallel AD imaging device is used, then conversion precision is improved, but device complexity increases due to large number of latch circuits
Solution Approach 1:
The imaging device is divided into two separate semiconductor chips: a first chip containing pixel circuits and a second chip containing analog-to-digital conversion circuits. This segmentation reduces the complexity of each individual chip while maintaining the high precision benefits of pixel-parallel AD conversion.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked chip architecture. By stacking the pixel circuit chip and ADC circuit chip vertically, the patent reduces in-plane complexity while enabling comprehensive failure detection across all latch circuits through the stacked structure.
2Reliability
If comprehensive failure detection is implemented for all latch circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The failure detection circuit performs comprehensive testing of all latch circuits before the chips are bonded together. By conducting failure detection in advance (before bonding), the patent ensures high reliability without adding complexity to the final integrated device structure.
Solution Approach 2:
The failure detection function is extracted as a separate circuit module within the ADC chip, allowing comprehensive testing of latch circuits without integrating the detection logic into every individual latch circuit, thus maintaining reliability while controlling overall device complexity.
3Manufacturing precision
If stacked chip structure is used, then manufacturing precision is improved through pre-bonding sorting, but device complexity increases
Solution Approach 1:
The patent implements failure detection and sorting of defective chips before the bonding process. By performing this preliminary sorting action, defective chips are identified and removed from the production flow before bonding, thereby improving manufacturing precision and yield without requiring complex post-bonding inspection systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables comprehensive failure detection of latch circuits and associated circuits in pixel-parallel AD imaging devices, improving yield and reducing costs by allowing for pre-bonding sorting of defective chips and preventing defects like white and black spots in captured images.
Implementation Method 1
a pixel circuit that includes a photoelectric conversion element
Data Source
AI summary
An imaging device according to the present disclosure has a stacked chip structure in which at least two semiconductor chips, that are a first semiconductor chip provided with a pixel circuit and a second semiconductor chip including an analog-to-digital (AD) conversion circuit which is provided so as to correspond to the pixel circuit, are stacked. The AD conversion circuit includes a latch circuit that retains a digital code after AD conversion and a transfer circuit that transfers the digital code after AD conversion. Further, a failure detection circuit for detecting a failure of the AD conversion circuit is provided. The failure detection circuit performs failure detection by writing a test pattern for failure detection into the latch circuit via the transfer circuit, then reading the test pattern from the latch circuit via the transfer circuit, and comparing the read test pattern with an expected value.